Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18958981 [patent_doc_number] => 20240047308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SEMICONDUCTOR PACKAGE HAVING COMPOSITE SEED-BARRIER LAYER AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/482006 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482006
Semiconductor package having composite seed-barrier layer and method of forming the same Oct 4, 2023 Issued
Array ( [id] => 19935114 [patent_doc_number] => 12308322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/447769 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 6703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447769
Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same Aug 9, 2023 Issued
Array ( [id] => 19285803 [patent_doc_number] => 20240222280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR PACKAGES AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/363995 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363995
SEMICONDUCTOR PACKAGES AND METHOD FOR FABRICATING THE SAME Aug 1, 2023 Pending
Array ( [id] => 18943499 [patent_doc_number] => 20240038638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => POWER ELECTRONICS MODULE [patent_app_type] => utility [patent_app_number] => 18/363311 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363311
Power electronics module Jul 31, 2023 Issued
Array ( [id] => 18774567 [patent_doc_number] => 20230369398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => MULTI-GATE DEVICE WITH AIR GAP SPACER AND FABRICATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/360974 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360974
Multi-gate device with air gap spacer and fabrication methods thereof Jul 27, 2023 Issued
Array ( [id] => 19612124 [patent_doc_number] => 12161019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Display apparatus including a heat-dissipation member and electronic device including the same [patent_app_type] => utility [patent_app_number] => 18/361769 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361769
Display apparatus including a heat-dissipation member and electronic device including the same Jul 27, 2023 Issued
Array ( [id] => 18757520 [patent_doc_number] => 20230360983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MODULE [patent_app_type] => utility [patent_app_number] => 18/351733 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351733
Electronic module Jul 12, 2023 Issued
Array ( [id] => 18729427 [patent_doc_number] => 20230343723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SOLDERED METALLIC RESERVOIRS FOR ENHANCED TRANSIENT AND STEADY-STATE THERMAL PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/216005 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216005 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216005
Soldered metallic reservoirs for enhanced transient and steady-state thermal performance Jun 28, 2023 Issued
Array ( [id] => 18712907 [patent_doc_number] => 20230335540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/338372 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338372 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338372
Method of fabricating semiconductor package including sub-interposer substrates Jun 20, 2023 Issued
Array ( [id] => 18898587 [patent_doc_number] => 20240014072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => NITROGEN PLASMA TREATMENT FOR BOTTOM-UP GROWTH [patent_app_type] => utility [patent_app_number] => 18/212352 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212352 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212352
NITROGEN PLASMA TREATMENT FOR BOTTOM-UP GROWTH Jun 20, 2023 Pending
Array ( [id] => 19887003 [patent_doc_number] => 12272736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => FinFET and gate-all-around FET with selective high-k oxide deposition [patent_app_type] => utility [patent_app_number] => 18/337767 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 9183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337767
FinFET and gate-all-around FET with selective high-k oxide deposition Jun 19, 2023 Issued
Array ( [id] => 18712821 [patent_doc_number] => 20230335454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/212160 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212160
Semiconductor device package Jun 19, 2023 Issued
Array ( [id] => 18696384 [patent_doc_number] => 20230326822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => Integrated Fan Out Method Utilizing a Filler-Free Insulating Material [patent_app_type] => utility [patent_app_number] => 18/335294 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335294
Integrated fan out device with a filler-free insulating material Jun 14, 2023 Issued
Array ( [id] => 18696313 [patent_doc_number] => 20230326749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR BURIED LAYER [patent_app_type] => utility [patent_app_number] => 18/203849 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203849
Semiconductor device in a containment structure including a buried layer May 30, 2023 Issued
Array ( [id] => 20118396 [patent_doc_number] => 12368114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor device package having warpage control and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/325205 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 2200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325205
Semiconductor device package having warpage control and method of forming the same May 29, 2023 Issued
Array ( [id] => 19796295 [patent_doc_number] => 12237264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Fusible structures [patent_app_type] => utility [patent_app_number] => 18/322481 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322481
Fusible structures May 22, 2023 Issued
Array ( [id] => 20496651 [patent_doc_number] => 12538542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Method of forming a MEOL contact structure [patent_app_type] => utility [patent_app_number] => 18/196833 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 9679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18196833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/196833
Method of forming a MEOL contact structure May 11, 2023 Issued
Array ( [id] => 18615821 [patent_doc_number] => 20230282560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/196590 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18196590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/196590
Semiconductor package with front side and back side redistribution structures and fabricating method thereof May 11, 2023 Issued
Array ( [id] => 18600244 [patent_doc_number] => 20230275045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/314984 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314984
Semiconductor package device with integrated inductor and manufacturing method thereof May 9, 2023 Issued
Array ( [id] => 18600222 [patent_doc_number] => 20230275023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CONNECTOR FOR IMPLEMENTING MULTI-FACETED INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 18/143170 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143170
Connector for implementing multi-faceted interconnection May 3, 2023 Issued
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