
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10447950
[patent_doc_number] => 20150332964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'SELF-LIMITING SILICIDE IN HIGHLY SCALED FIN TECHNOLOGY'
[patent_app_type] => utility
[patent_app_number] => 14/281444
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281444
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281444 | Self-limiting silicide in highly scaled fin technology | May 18, 2014 | Issued |
Array
(
[id] => 10447948
[patent_doc_number] => 20150332963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'T-SHAPED CONTACTS FOR SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/281454
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4491
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281454
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281454 | T-shaped contacts for semiconductor device | May 18, 2014 | Issued |
Array
(
[id] => 10448158
[patent_doc_number] => 20150333172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS'
[patent_app_type] => utility
[patent_app_number] => 14/281364
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281364
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281364 | Method to controllably etch silicon recess for ultra shallow junctions | May 18, 2014 | Issued |
Array
(
[id] => 10106635
[patent_doc_number] => 09142418
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-09-22
[patent_title] => 'Double/multiple fin structure for FinFET devices'
[patent_app_type] => utility
[patent_app_number] => 14/281726
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 2941
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281726
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281726 | Double/multiple fin structure for FinFET devices | May 18, 2014 | Issued |
Array
(
[id] => 10447999
[patent_doc_number] => 20150333014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT'
[patent_app_type] => utility
[patent_app_number] => 14/281362
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4459
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281362
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281362 | Semiconductor devices and methods for backside photo alignment | May 18, 2014 | Issued |
Array
(
[id] => 10597468
[patent_doc_number] => 09318564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'High density static random access memory array having advanced metal patterning'
[patent_app_type] => utility
[patent_app_number] => 14/281710
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7039
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281710
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281710 | High density static random access memory array having advanced metal patterning | May 18, 2014 | Issued |
Array
(
[id] => 10583938
[patent_doc_number] => 09306066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Method and apparatus of stressed FIN NMOS FinFET'
[patent_app_type] => utility
[patent_app_number] => 14/281660
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 6873
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281660
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281660 | Method and apparatus of stressed FIN NMOS FinFET | May 18, 2014 | Issued |
Array
(
[id] => 10971733
[patent_doc_number] => 20140374768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-25
[patent_title] => 'HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON'
[patent_app_type] => utility
[patent_app_number] => 14/256790
[patent_app_country] => US
[patent_app_date] => 2014-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3889
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256790
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/256790 | High quality GaN high-voltage HFETs on silicon | Apr 17, 2014 | Issued |
Array
(
[id] => 10047503
[patent_doc_number] => 09087908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-21
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/255124
[patent_app_country] => US
[patent_app_date] => 2014-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 35
[patent_no_of_words] => 22944
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255124
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/255124 | Semiconductor device | Apr 16, 2014 | Issued |
Array
(
[id] => 9888909
[patent_doc_number] => 08975163
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-03-10
[patent_title] => 'Laser-dominated laser scribing and plasma etch hybrid wafer dicing'
[patent_app_type] => utility
[patent_app_number] => 14/249891
[patent_app_country] => US
[patent_app_date] => 2014-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 11204
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14249891
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/249891 | Laser-dominated laser scribing and plasma etch hybrid wafer dicing | Apr 9, 2014 | Issued |
Array
(
[id] => 12954382
[patent_doc_number] => 09837609
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-05
[patent_title] => Method for manufacturing an organic electronic device and organic electronic device
[patent_app_type] => utility
[patent_app_number] => 14/779202
[patent_app_country] => US
[patent_app_date] => 2014-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 12
[patent_no_of_words] => 8057
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14779202
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/779202 | Method for manufacturing an organic electronic device and organic electronic device | Mar 24, 2014 | Issued |
Array
(
[id] => 9594555
[patent_doc_number] => 20140191232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-10
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/207750
[patent_app_country] => US
[patent_app_date] => 2014-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 17022
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14207750
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/207750 | Semiconductor device | Mar 12, 2014 | Issued |
Array
(
[id] => 10155557
[patent_doc_number] => 09187312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-17
[patent_title] => 'Integrated bondline spacers for wafer level packaged circuit devices'
[patent_app_type] => utility
[patent_app_number] => 14/202756
[patent_app_country] => US
[patent_app_date] => 2014-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 5599
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14202756
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/202756 | Integrated bondline spacers for wafer level packaged circuit devices | Mar 9, 2014 | Issued |
Array
(
[id] => 9569292
[patent_doc_number] => 20140187005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, ELECTRONIC DEVICE AND VEHICLE'
[patent_app_type] => utility
[patent_app_number] => 14/196986
[patent_app_country] => US
[patent_app_date] => 2014-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6670
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196986
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/196986 | Semiconductor device, manufacturing method thereof, electronic device and vehicle | Mar 3, 2014 | Issued |
Array
(
[id] => 12516039
[patent_doc_number] => 10002814
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-19
[patent_title] => Apparatuses and methods to enhance passivation and ILD reliability
[patent_app_type] => utility
[patent_app_number] => 14/195422
[patent_app_country] => US
[patent_app_date] => 2014-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 4066
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195422
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/195422 | Apparatuses and methods to enhance passivation and ILD reliability | Mar 2, 2014 | Issued |
Array
(
[id] => 10616901
[patent_doc_number] => 09336344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-10
[patent_title] => 'Coarse grid design methods and structures'
[patent_app_type] => utility
[patent_app_number] => 14/187088
[patent_app_country] => US
[patent_app_date] => 2014-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 9138
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187088
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/187088 | Coarse grid design methods and structures | Feb 20, 2014 | Issued |
Array
(
[id] => 9565459
[patent_doc_number] => 20140183172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'LASER CRYSTALLIZATION SYSTEM AND METHOD OF MANUFACTURING DISPLAY APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/184114
[patent_app_country] => US
[patent_app_date] => 2014-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6379
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184114
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/184114 | Laser crystallization system and method of manufacturing display apparatus using the same | Feb 18, 2014 | Issued |
Array
(
[id] => 10343734
[patent_doc_number] => 20150228739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-13
[patent_title] => 'SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/177164
[patent_app_country] => US
[patent_app_date] => 2014-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6446
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177164
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/177164 | Split gate embedded memory technology and manufacturing method thereof | Feb 9, 2014 | Issued |
Array
(
[id] => 10112201
[patent_doc_number] => 09147619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-29
[patent_title] => 'Organic light-emitting display panel'
[patent_app_type] => utility
[patent_app_number] => 14/176589
[patent_app_country] => US
[patent_app_date] => 2014-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 14427
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176589
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/176589 | Organic light-emitting display panel | Feb 9, 2014 | Issued |
Array
(
[id] => 10336730
[patent_doc_number] => 20150221735
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'Method of Forming a Trench Using Epitaxial Lateral Overgrowth and Deep Vertical Trench Structure'
[patent_app_type] => utility
[patent_app_number] => 14/174185
[patent_app_country] => US
[patent_app_date] => 2014-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6341
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174185
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/174185 | Method of forming a trench using epitaxial lateral overgrowth and deep vertical trench structure | Feb 5, 2014 | Issued |