
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8914014
[patent_doc_number] => 20130175639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length'
[patent_app_type] => utility
[patent_app_number] => 13/774970
[patent_app_country] => US
[patent_app_date] => 2013-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13995
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774970
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774970 | Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length | Feb 21, 2013 | Issued |
Array
(
[id] => 8888576
[patent_doc_number] => 20130161760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings'
[patent_app_type] => utility
[patent_app_number] => 13/774919
[patent_app_country] => US
[patent_app_date] => 2013-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13675
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774919
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774919 | Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings | Feb 21, 2013 | Abandoned |
Array
(
[id] => 8901273
[patent_doc_number] => 20130168777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes'
[patent_app_type] => utility
[patent_app_number] => 13/774940
[patent_app_country] => US
[patent_app_date] => 2013-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13570
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774940
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774940 | Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes | Feb 21, 2013 | Abandoned |
Array
(
[id] => 8901276
[patent_doc_number] => 20130168778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track'
[patent_app_type] => utility
[patent_app_number] => 13/774954
[patent_app_country] => US
[patent_app_date] => 2013-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 13625
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774954
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774954 | Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track | Feb 21, 2013 | Abandoned |
Array
(
[id] => 8850885
[patent_doc_number] => 20130140560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-06
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/753582
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 16809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753582
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753582 | Semiconductor device | Jan 29, 2013 | Issued |
Array
(
[id] => 9893180
[patent_doc_number] => 20150048379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-19
[patent_title] => 'Light Emitting Diode and Manufacturing Method Therefor'
[patent_app_type] => utility
[patent_app_number] => 14/369930
[patent_app_country] => US
[patent_app_date] => 2013-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5778
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14369930
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/369930 | Light emitting diode and manufacturing method therefor | Jan 6, 2013 | Issued |
Array
(
[id] => 9205494
[patent_doc_number] => 20140004671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/709614
[patent_app_country] => US
[patent_app_date] => 2012-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 6905
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709614
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/709614 | Super-self-aligned Trench-DMOS structure and method | Dec 9, 2012 | Issued |
Array
(
[id] => 8755672
[patent_doc_number] => 20130089977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'METHOD FOR FORMING HIGH DENSITY PATTERNS'
[patent_app_type] => utility
[patent_app_number] => 13/690266
[patent_app_country] => US
[patent_app_date] => 2012-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5007
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690266
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/690266 | Method for forming high density patterns | Nov 29, 2012 | Issued |
Array
(
[id] => 9704450
[patent_doc_number] => 08829520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 13/685638
[patent_app_country] => US
[patent_app_date] => 2012-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2955
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685638
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/685638 | Thin film transistor | Nov 25, 2012 | Issued |
Array
(
[id] => 8888408
[patent_doc_number] => 20130161592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/685190
[patent_app_country] => US
[patent_app_date] => 2012-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5679
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685190
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/685190 | Organic light emitting diode display and manufacturing method thereof | Nov 25, 2012 | Issued |
Array
(
[id] => 9303721
[patent_doc_number] => 20140042395
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'Thin Film Transistor Substrate and Method for Manufacturing the Same and Organic Light Emitting Device Using the Same'
[patent_app_type] => utility
[patent_app_number] => 13/685572
[patent_app_country] => US
[patent_app_date] => 2012-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8437
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685572
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/685572 | Thin film transistor substrate and method for manufacturing the same and organic light emitting device using the same | Nov 25, 2012 | Issued |
Array
(
[id] => 9286837
[patent_doc_number] => 08643168
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-02-04
[patent_title] => 'Integrated circuit package with input capacitance compensation'
[patent_app_type] => utility
[patent_app_number] => 13/685385
[patent_app_country] => US
[patent_app_date] => 2012-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685385
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/685385 | Integrated circuit package with input capacitance compensation | Nov 25, 2012 | Issued |
Array
(
[id] => 9662206
[patent_doc_number] => 08809181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Multi-solder techniques and configurations for integrated circuit package assembly'
[patent_app_type] => utility
[patent_app_number] => 13/670687
[patent_app_country] => US
[patent_app_date] => 2012-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6778
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670687
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/670687 | Multi-solder techniques and configurations for integrated circuit package assembly | Nov 6, 2012 | Issued |
Array
(
[id] => 9460473
[patent_doc_number] => 20140124899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/667458
[patent_app_country] => US
[patent_app_date] => 2012-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5555
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667458
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667458 | Integrated bondline spacers for wafer level packaged circuit devices | Nov 1, 2012 | Issued |
Array
(
[id] => 9692585
[patent_doc_number] => 08823187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-02
[patent_title] => 'Semiconductor package, semiconductor package manufacturing method and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/667504
[patent_app_country] => US
[patent_app_date] => 2012-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 26
[patent_no_of_words] => 10132
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667504
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667504 | Semiconductor package, semiconductor package manufacturing method and semiconductor device | Nov 1, 2012 | Issued |
Array
(
[id] => 8811970
[patent_doc_number] => 20130113015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'Substrate, Light Emitting Device and Method for Manufacturing Substrate'
[patent_app_type] => utility
[patent_app_number] => 13/667540
[patent_app_country] => US
[patent_app_date] => 2012-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10552
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667540
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667540 | Substrate, light emitting device and method for manufacturing substrate | Nov 1, 2012 | Issued |
Array
(
[id] => 9460512
[patent_doc_number] => 20140124938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'STRESS RELIEF FOR PLASTIC ENCAPSULATED DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/667403
[patent_app_country] => US
[patent_app_date] => 2012-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1548
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667403
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667403 | Stress relief for plastic encapsulated devices | Nov 1, 2012 | Issued |
Array
(
[id] => 9483661
[patent_doc_number] => 08729613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-20
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/649580
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 35
[patent_no_of_words] => 22946
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649580
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649580 | Semiconductor device | Oct 10, 2012 | Issued |
Array
(
[id] => 9216745
[patent_doc_number] => 08629548
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-01-14
[patent_title] => 'Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node'
[patent_app_type] => utility
[patent_app_number] => 13/649547
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 13563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649547
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649547 | Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node | Oct 10, 2012 | Issued |
Array
(
[id] => 9239760
[patent_doc_number] => 08604555
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-12-10
[patent_title] => 'Semiconductor structure and manufacturing method of the same'
[patent_app_type] => utility
[patent_app_number] => 13/649232
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 40
[patent_no_of_words] => 7530
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649232
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649232 | Semiconductor structure and manufacturing method of the same | Oct 10, 2012 | Issued |