| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4469243
[patent_doc_number] => 07943420
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-17
[patent_title] => 'Single mask adder phase change memory element'
[patent_app_type] => utility
[patent_app_number] => 12/625855
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 4712
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/943/07943420.pdf
[firstpage_image] =>[orig_patent_app_number] => 12625855
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/625855 | Single mask adder phase change memory element | Nov 24, 2009 | Issued |
Array
(
[id] => 10888017
[patent_doc_number] => 08912012
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Magnetic tunnel junction device and fabrication'
[patent_app_type] => utility
[patent_app_number] => 12/626269
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7120
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12626269
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/626269 | Magnetic tunnel junction device and fabrication | Nov 24, 2009 | Issued |
Array
(
[id] => 6582775
[patent_doc_number] => 20100129939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'USING OPTICAL METROLOGY FOR WITHIN WAFER FEED FORWARD PROCESS CONTROL'
[patent_app_type] => utility
[patent_app_number] => 12/625489
[patent_app_country] => US
[patent_app_date] => 2009-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12035
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20100129939.pdf
[firstpage_image] =>[orig_patent_app_number] => 12625489
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/625489 | Using optical metrology for within wafer feed forward process control | Nov 23, 2009 | Issued |
Array
(
[id] => 7490401
[patent_doc_number] => 08030158
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Method for fabricating contacts in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/624278
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2867
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/030/08030158.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624278
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624278 | Method for fabricating contacts in semiconductor device | Nov 22, 2009 | Issued |
Array
(
[id] => 6295184
[patent_doc_number] => 20100065970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 12/624215
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5957
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20100065970.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624215
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624215 | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods | Nov 22, 2009 | Issued |
Array
(
[id] => 4644877
[patent_doc_number] => 08022483
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-20
[patent_title] => 'Semiconductor and manufacturing method for the same'
[patent_app_type] => utility
[patent_app_number] => 12/623803
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2694
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/022/08022483.pdf
[firstpage_image] =>[orig_patent_app_number] => 12623803
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/623803 | Semiconductor and manufacturing method for the same | Nov 22, 2009 | Issued |
Array
(
[id] => 4479404
[patent_doc_number] => 07906782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-15
[patent_title] => 'Liquid crystal display device'
[patent_app_type] => utility
[patent_app_number] => 12/591502
[patent_app_country] => US
[patent_app_date] => 2009-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 22
[patent_no_of_words] => 3410
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/906/07906782.pdf
[firstpage_image] =>[orig_patent_app_number] => 12591502
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/591502 | Liquid crystal display device | Nov 19, 2009 | Issued |
Array
(
[id] => 6294967
[patent_doc_number] => 20100065882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'GLASS FOR COVERING OPTICAL ELEMENT, GLASS-COVERED LIGHT-EMITTING ELEMENT AND GLASS-COVERED LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/621572
[patent_app_country] => US
[patent_app_date] => 2009-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7698
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20100065882.pdf
[firstpage_image] =>[orig_patent_app_number] => 12621572
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/621572 | Glass for covering optical element, glass-covered light-emitting element and glass-covered light-emitting device | Nov 18, 2009 | Issued |
Array
(
[id] => 6220940
[patent_doc_number] => 20100055871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'MEMORY IN LOGIC CELL'
[patent_app_type] => utility
[patent_app_number] => 12/615961
[patent_app_country] => US
[patent_app_date] => 2009-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6732
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20100055871.pdf
[firstpage_image] =>[orig_patent_app_number] => 12615961
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/615961 | Memory in logic cell | Nov 9, 2009 | Issued |
Array
(
[id] => 6216070
[patent_doc_number] => 20100052126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'APPARATUS AND METHOD FOR USE IN MOUNTING ELECTRONIC ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 12/614989
[patent_app_country] => US
[patent_app_date] => 2009-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10306
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20100052126.pdf
[firstpage_image] =>[orig_patent_app_number] => 12614989
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/614989 | Apparatus and method for use in mounting electronic elements | Nov 8, 2009 | Issued |
Array
(
[id] => 4568989
[patent_doc_number] => 07858487
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Method and apparatus for indicating directionality in integrated circuit manufacturing'
[patent_app_type] => utility
[patent_app_number] => 12/614890
[patent_app_country] => US
[patent_app_date] => 2009-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6505
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/858/07858487.pdf
[firstpage_image] =>[orig_patent_app_number] => 12614890
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/614890 | Method and apparatus for indicating directionality in integrated circuit manufacturing | Nov 8, 2009 | Issued |
Array
(
[id] => 8653492
[patent_doc_number] => 08373241
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-12
[patent_title] => 'Antireflective hard mask compositions'
[patent_app_type] => utility
[patent_app_number] => 12/582673
[patent_app_country] => US
[patent_app_date] => 2009-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 11432
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12582673
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/582673 | Antireflective hard mask compositions | Oct 19, 2009 | Issued |
Array
(
[id] => 4546515
[patent_doc_number] => 07960219
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-14
[patent_title] => 'Thin-film transistor substrate and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 12/575570
[patent_app_country] => US
[patent_app_date] => 2009-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 24
[patent_no_of_words] => 7657
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/960/07960219.pdf
[firstpage_image] =>[orig_patent_app_number] => 12575570
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/575570 | Thin-film transistor substrate and method of fabricating the same | Oct 7, 2009 | Issued |
Array
(
[id] => 7801485
[patent_doc_number] => 08129757
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length'
[patent_app_type] => utility
[patent_app_number] => 12/572239
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 14894
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 521
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/129/08129757.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572239
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572239 | Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length | Sep 30, 2009 | Issued |
Array
(
[id] => 6336227
[patent_doc_number] => 20100019287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing'
[patent_app_type] => utility
[patent_app_number] => 12/572225
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14864
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20100019287.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572225
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572225 | Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length | Sep 30, 2009 | Issued |
Array
(
[id] => 6648828
[patent_doc_number] => 20100037195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region'
[patent_app_type] => utility
[patent_app_number] => 12/572194
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14916
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20100037195.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572194
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572194 | Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment | Sep 30, 2009 | Issued |
Array
(
[id] => 7680897
[patent_doc_number] => 20100023911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors'
[patent_app_type] => utility
[patent_app_number] => 12/572201
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14884
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20100023911.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572201
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572201 | Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size | Sep 30, 2009 | Issued |
Array
(
[id] => 6336219
[patent_doc_number] => 20100019286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing'
[patent_app_type] => utility
[patent_app_number] => 12/572218
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14777
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20100019286.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572218
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572218 | Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor | Sep 30, 2009 | Issued |
Array
(
[id] => 8375766
[patent_doc_number] => 08258552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-04
[patent_title] => 'Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends'
[patent_app_type] => utility
[patent_app_number] => 12/572243
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 14940
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 725
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12572243
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572243 | Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends | Sep 30, 2009 | Issued |
Array
(
[id] => 6599539
[patent_doc_number] => 20100032724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors'
[patent_app_type] => utility
[patent_app_number] => 12/572022
[patent_app_country] => US
[patent_app_date] => 2009-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14833
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20100032724.pdf
[firstpage_image] =>[orig_patent_app_number] => 12572022
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/572022 | Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region | Sep 30, 2009 | Issued |