Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20259066 [patent_doc_number] => 12431431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Conductive structure interconnects with downward projections [patent_app_type] => utility [patent_app_number] => 17/804919 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804919
Conductive structure interconnects with downward projections May 31, 2022 Issued
Array ( [id] => 19444692 [patent_doc_number] => 12094984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/825359 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 6429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825359
Semiconductor device May 25, 2022 Issued
Array ( [id] => 20082582 [patent_doc_number] => 12356682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor structure with conductive structure [patent_app_type] => utility [patent_app_number] => 17/749359 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 54 [patent_no_of_words] => 4189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749359
Semiconductor structure with conductive structure May 19, 2022 Issued
Array ( [id] => 18789279 [patent_doc_number] => 20230377929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ALIGNMENT TARGETS ON OPPOSING SUBSTRATE SIDES [patent_app_type] => utility [patent_app_number] => 17/663858 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663858
Alignment of targets on opposite sides of a substrate May 17, 2022 Issued
Array ( [id] => 17810905 [patent_doc_number] => 20220262740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => ELECTRONIC ASSEMBLY, ELECTRONIC APPARATUS INCLUDING THE SAME AND METHOD FOR FABRICATING ELECTRONIC ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/737285 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737285
Method for fabricating electronic assembly including a magnetic field shielding film May 4, 2022 Issued
Array ( [id] => 17993314 [patent_doc_number] => 20220359351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MICROELECTRONICS PACKAGE ASSEMBLIES AND PROCESSES FOR MAKING [patent_app_type] => utility [patent_app_number] => 17/737564 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737564
Microelectronics package assemblies and processes for making May 4, 2022 Issued
Array ( [id] => 18507651 [patent_doc_number] => 11705480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Optoelectronic device with electrodes forming an outer boundary beyond an outer boundary of an epitaxial stack [patent_app_type] => utility [patent_app_number] => 17/733262 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 8445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733262
Optoelectronic device with electrodes forming an outer boundary beyond an outer boundary of an epitaxial stack Apr 28, 2022 Issued
Array ( [id] => 17795756 [patent_doc_number] => 20220254848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/732526 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732526
Display device having power line Apr 28, 2022 Issued
Array ( [id] => 19409136 [patent_doc_number] => 20240292647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/022153 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18022153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/022153
Light-emitting device with electron transport layer and intervening layer, manufacturing method thereof, display substrate and display apparatus Apr 27, 2022 Issued
Array ( [id] => 17782182 [patent_doc_number] => 20220248532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Opposing Planar Electrically Conductive Surfaces Connected for Establishing a Two-Dimensional Electric Connection Area Between Component Carrier Stacks [patent_app_type] => utility [patent_app_number] => 17/660258 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660258
Electrically connected component carrier stacks with respective cavities and method of manufacturing the same Apr 21, 2022 Issued
Array ( [id] => 19428215 [patent_doc_number] => 12087648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Seal ring structure with zigzag patterns and method forming same [patent_app_type] => utility [patent_app_number] => 17/659048 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 7847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659048
Seal ring structure with zigzag patterns and method forming same Apr 12, 2022 Issued
Array ( [id] => 18704772 [patent_doc_number] => 11791289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Semiconductor package substrate with a smooth groove about a perimeter of a semiconductor die [patent_app_type] => utility [patent_app_number] => 17/719235 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7035 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719235
Semiconductor package substrate with a smooth groove about a perimeter of a semiconductor die Apr 11, 2022 Issued
Array ( [id] => 18238920 [patent_doc_number] => 20230071231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/714450 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714450
Semiconductor device channel layers stacked vertically and method of fabricating the same Apr 5, 2022 Issued
Array ( [id] => 18161999 [patent_doc_number] => 20230028591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => Adjusting the Profile of Source/Drain Regions to Reduce Leakage [patent_app_type] => utility [patent_app_number] => 17/657822 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657822
Method of forming source/drain regions with quadrilateral layers Apr 3, 2022 Issued
Array ( [id] => 20598272 [patent_doc_number] => 12582013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Configurations for metal posts for dual side mold modules [patent_app_type] => utility [patent_app_number] => 17/706883 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 3228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706883
Configurations for metal posts for dual side mold modules Mar 28, 2022 Issued
Array ( [id] => 19741331 [patent_doc_number] => 12218179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Display device having light blocking part in non-display area and tiled display device including the same [patent_app_type] => utility [patent_app_number] => 17/701207 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701207 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701207
Display device having light blocking part in non-display area and tiled display device including the same Mar 21, 2022 Issued
Array ( [id] => 20082518 [patent_doc_number] => 12356615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device including vertical channel pattern surrounded by protection pattern [patent_app_type] => utility [patent_app_number] => 17/693875 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693875 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693875
Semiconductor device including vertical channel pattern surrounded by protection pattern Mar 13, 2022 Issued
Array ( [id] => 18913057 [patent_doc_number] => 11876044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Method for activating backup unit through fuse element [patent_app_type] => utility [patent_app_number] => 17/691932 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6138 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691932
Method for activating backup unit through fuse element Mar 9, 2022 Issued
Array ( [id] => 17692248 [patent_doc_number] => 20220199541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => Dual-sided Routing in 3D SiP Structure [patent_app_type] => utility [patent_app_number] => 17/690206 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690206
Dual-sided routing in 3D SiP structure Mar 8, 2022 Issued
Array ( [id] => 20204154 [patent_doc_number] => 12406938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Methods of forming alignment structure with trenches for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/689413 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 2261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689413
Methods of forming alignment structure with trenches for semiconductor devices Mar 7, 2022 Issued
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