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[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors'
[patent_app_type] => utility
[patent_app_number] => 12/563074
[patent_app_country] => US
[patent_app_date] => 2009-09-18
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[patent_no_of_words] => 14890
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[pdf_file] => publications/A1/0011/20100011332.pdf
[firstpage_image] =>[orig_patent_app_number] => 12563074
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/563074 | Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment | Sep 17, 2009 | Issued |
