Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7703341 [patent_doc_number] => 08089098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment' [patent_app_type] => utility [patent_app_number] => 12/563063 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 15010 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/089/08089098.pdf [firstpage_image] =>[orig_patent_app_number] => 12563063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563063
Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment Sep 17, 2009 Issued
Array ( [id] => 4532089 [patent_doc_number] => 07923757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level' [patent_app_type] => utility [patent_app_number] => 12/563066 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14952 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 32 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923757.pdf [firstpage_image] =>[orig_patent_app_number] => 12563066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563066
Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level Sep 17, 2009 Issued
Array ( [id] => 6463805 [patent_doc_number] => 20100006950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors' [patent_app_type] => utility [patent_app_number] => 12/563051 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14759 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006950.pdf [firstpage_image] =>[orig_patent_app_number] => 12563051 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563051
Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch Sep 17, 2009 Issued
Array ( [id] => 6463291 [patent_doc_number] => 20100006893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/562029 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8615 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006893.pdf [firstpage_image] =>[orig_patent_app_number] => 12562029 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562029
Strained layers within semiconductor buffer structures Sep 16, 2009 Issued
Array ( [id] => 6463365 [patent_doc_number] => 20100006903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Portion Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions' [patent_app_type] => utility [patent_app_number] => 12/561246 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14827 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006903.pdf [firstpage_image] =>[orig_patent_app_number] => 12561246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561246
Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch Sep 15, 2009 Issued
Array ( [id] => 6463354 [patent_doc_number] => 20100006901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions' [patent_app_type] => utility [patent_app_number] => 12/561238 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14733 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006901.pdf [firstpage_image] =>[orig_patent_app_number] => 12561238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561238
Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments Sep 15, 2009 Issued
Array ( [id] => 4614131 [patent_doc_number] => 07989848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground' [patent_app_type] => utility [patent_app_number] => 12/561243 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14793 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989848.pdf [firstpage_image] =>[orig_patent_app_number] => 12561243 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561243
Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground Sep 15, 2009 Issued
Array ( [id] => 4614126 [patent_doc_number] => 07989847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths' [patent_app_type] => utility [patent_app_number] => 12/561234 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14896 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989847.pdf [firstpage_image] =>[orig_patent_app_number] => 12561234 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561234
Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths Sep 15, 2009 Issued
Array ( [id] => 6512137 [patent_doc_number] => 20100011327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors' [patent_app_type] => utility [patent_app_number] => 12/561229 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14840 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011327.pdf [firstpage_image] =>[orig_patent_app_number] => 12561229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561229
Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment Sep 15, 2009 Issued
Array ( [id] => 4499126 [patent_doc_number] => 07948012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment' [patent_app_type] => utility [patent_app_number] => 12/561224 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14890 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948012.pdf [firstpage_image] =>[orig_patent_app_number] => 12561224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561224
Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment Sep 15, 2009 Issued
Array ( [id] => 6463321 [patent_doc_number] => 20100006897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors' [patent_app_type] => utility [patent_app_number] => 12/561220 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14834 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006897.pdf [firstpage_image] =>[orig_patent_app_number] => 12561220 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561220
Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch Sep 15, 2009 Issued
Array ( [id] => 4517738 [patent_doc_number] => 07932544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions' [patent_app_type] => utility [patent_app_number] => 12/561207 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 14779 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932544.pdf [firstpage_image] =>[orig_patent_app_number] => 12561207 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561207
Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions Sep 15, 2009 Issued
Array ( [id] => 6463331 [patent_doc_number] => 20100006899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors' [patent_app_type] => utility [patent_app_number] => 12/561247 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14751 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006899.pdf [firstpage_image] =>[orig_patent_app_number] => 12561247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561247
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level Sep 15, 2009 Issued
Array ( [id] => 6464093 [patent_doc_number] => 20100006986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions' [patent_app_type] => utility [patent_app_number] => 12/561216 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14884 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006986.pdf [firstpage_image] =>[orig_patent_app_number] => 12561216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561216
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions Sep 15, 2009 Issued
Array ( [id] => 5465147 [patent_doc_number] => 20090325347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'APPARATUSES AND METHODS TO ENHANCE PASSIVATION AND ILD RELIABILITY' [patent_app_type] => utility [patent_app_number] => 12/554523 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4045 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12554523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554523
Apparatuses and methods to enhance passivation and ILD reliability Sep 3, 2009 Issued
Array ( [id] => 83422 [patent_doc_number] => 07741160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-22 [patent_title] => 'Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate' [patent_app_type] => utility [patent_app_number] => 12/535624 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7755 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741160.pdf [firstpage_image] =>[orig_patent_app_number] => 12535624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535624
Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate Aug 3, 2009 Issued
Array ( [id] => 5367918 [patent_doc_number] => 20090305477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'INTEGRATED CIRCUIT ARRANGEMENT WITH NPN AND PNP BIPOLAR TRANSISTORS AND CORRESPONDING PRODUCTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/512660 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5160 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20090305477.pdf [firstpage_image] =>[orig_patent_app_number] => 12512660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512660
Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method Jul 29, 2009 Issued
Array ( [id] => 5313531 [patent_doc_number] => 20090278129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/506872 [patent_app_country] => US [patent_app_date] => 2009-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 5966 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20090278129.pdf [firstpage_image] =>[orig_patent_app_number] => 12506872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/506872
Liquid crystal display device and method of fabricating the same Jul 20, 2009 Issued
Array ( [id] => 8294347 [patent_doc_number] => 08222130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'High voltage device' [patent_app_type] => utility [patent_app_number] => 12/500620 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7811 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12500620 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500620
High voltage device Jul 9, 2009 Issued
Array ( [id] => 8104823 [patent_doc_number] => 08154061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Bottom gate thin film transistor and active array substrate' [patent_app_type] => utility [patent_app_number] => 12/500609 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3391 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154061.pdf [firstpage_image] =>[orig_patent_app_number] => 12500609 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500609
Bottom gate thin film transistor and active array substrate Jul 9, 2009 Issued
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