Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6600906 [patent_doc_number] => 20100032830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'THREE-DIMENSIONAL CONDUCTING STRUCTURE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/500780 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5357 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20100032830.pdf [firstpage_image] =>[orig_patent_app_number] => 12500780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500780
Three-dimensional conducting structure and method of fabricating the same Jul 9, 2009 Issued
Array ( [id] => 6215745 [patent_doc_number] => 20100051933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/500506 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20100051933.pdf [firstpage_image] =>[orig_patent_app_number] => 12500506 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500506
Thin film transistor array substrate and method of fabricating the same Jul 8, 2009 Issued
Array ( [id] => 6502168 [patent_doc_number] => 20100012997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => '3-DIMENSIONAL FLASH MEMORY DEVICE, METHOD OF FABRICATION AND METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 12/499980 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20100012997.pdf [firstpage_image] =>[orig_patent_app_number] => 12499980 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499980
3-dimensional flash memory device, method of fabrication and method of operation Jul 8, 2009 Issued
Array ( [id] => 8017139 [patent_doc_number] => 08138072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Semiconductor structures and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 12/500022 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/138/08138072.pdf [firstpage_image] =>[orig_patent_app_number] => 12500022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500022
Semiconductor structures and methods of manufacture Jul 8, 2009 Issued
Array ( [id] => 6130817 [patent_doc_number] => 20110006440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'SYSTEM AND METHOD TO REDUCE THE BONDWIRE/TRACE INDUCTANCE' [patent_app_type] => utility [patent_app_number] => 12/500046 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1274 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20110006440.pdf [firstpage_image] =>[orig_patent_app_number] => 12500046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500046
System and method to reduce the bondwire/trace inductance Jul 8, 2009 Issued
Array ( [id] => 4619529 [patent_doc_number] => 07999249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Nitride semiconductor light emitting device with surface texture and its manufacture' [patent_app_type] => utility [patent_app_number] => 12/500155 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999249.pdf [firstpage_image] =>[orig_patent_app_number] => 12500155 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500155
Nitride semiconductor light emitting device with surface texture and its manufacture Jul 8, 2009 Issued
Array ( [id] => 5558323 [patent_doc_number] => 20090269900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/500343 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9592 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20090269900.pdf [firstpage_image] =>[orig_patent_app_number] => 12500343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500343
Semiconductor device and manufacture method thereof Jul 8, 2009 Issued
Array ( [id] => 8410719 [patent_doc_number] => 08274117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Method for manufacturing semiconductor device, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/500277 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 5846 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12500277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500277
Method for manufacturing semiconductor device, and semiconductor device Jul 8, 2009 Issued
Array ( [id] => 6463275 [patent_doc_number] => 20100006890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'ESD Protection Device with Increased Holding Voltage During Normal Operation' [patent_app_type] => utility [patent_app_number] => 12/500170 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6326 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006890.pdf [firstpage_image] =>[orig_patent_app_number] => 12500170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500170
ESD protection device with increased holding voltage during normal operation Jul 8, 2009 Issued
Array ( [id] => 8713832 [patent_doc_number] => 08399974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Methods of dicing stacked shingled strip constructions to form stacked die packages' [patent_app_type] => utility [patent_app_number] => 12/500415 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5004 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12500415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500415
Methods of dicing stacked shingled strip constructions to form stacked die packages Jul 8, 2009 Issued
Array ( [id] => 8082933 [patent_doc_number] => 08148786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate' [patent_app_type] => utility [patent_app_number] => 12/493291 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3333 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/148/08148786.pdf [firstpage_image] =>[orig_patent_app_number] => 12493291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493291
Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate Jun 28, 2009 Issued
Array ( [id] => 5488224 [patent_doc_number] => 20090289295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Semiconductor Device and Method of Fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/472206 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3871 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289295.pdf [firstpage_image] =>[orig_patent_app_number] => 12472206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472206
Semiconductor Device and Method of Fabricating the same May 25, 2009 Abandoned
Array ( [id] => 5488303 [patent_doc_number] => 20090289374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MODULE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE MODULE' [patent_app_type] => utility [patent_app_number] => 12/471449 [patent_app_country] => US [patent_app_date] => 2009-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289374.pdf [firstpage_image] =>[orig_patent_app_number] => 12471449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471449
Semiconductor device, semiconductor device module, and method for manufacturing the semiconductor device module May 24, 2009 Issued
Array ( [id] => 5549897 [patent_doc_number] => 20090283883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Semiconductor device using lead frame' [patent_app_type] => utility [patent_app_number] => 12/453660 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283883.pdf [firstpage_image] =>[orig_patent_app_number] => 12453660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453660
Semiconductor device using lead frame May 17, 2009 Issued
Array ( [id] => 5549891 [patent_doc_number] => 20090283877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/466656 [patent_app_country] => US [patent_app_date] => 2009-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6681 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283877.pdf [firstpage_image] =>[orig_patent_app_number] => 12466656 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/466656
Semiconductor device and manufacturing method thereof May 14, 2009 Issued
Array ( [id] => 5383152 [patent_doc_number] => 20090224396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Oversized Contacts and Vias in Semiconductor Chip Defined by Linearly Constrained Topology' [patent_app_type] => utility [patent_app_number] => 12/466341 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8779 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20090224396.pdf [firstpage_image] =>[orig_patent_app_number] => 12466341 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/466341
Oversized contacts and vias in semiconductor chip defined by linearly constrained topology May 13, 2009 Issued
Array ( [id] => 4485651 [patent_doc_number] => 07883948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Method and structure for reducing induced mechanical stresses' [patent_app_type] => utility [patent_app_number] => 12/465817 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883948.pdf [firstpage_image] =>[orig_patent_app_number] => 12465817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/465817
Method and structure for reducing induced mechanical stresses May 13, 2009 Issued
Array ( [id] => 13437 [patent_doc_number] => 07807501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Integrated circuit package and apparatus and method of producing an integrated circuit package' [patent_app_type] => utility [patent_app_number] => 12/466248 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3094 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/807/07807501.pdf [firstpage_image] =>[orig_patent_app_number] => 12466248 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/466248
Integrated circuit package and apparatus and method of producing an integrated circuit package May 13, 2009 Issued
Array ( [id] => 7978601 [patent_doc_number] => 08072048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/453037 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 61 [patent_no_of_words] => 16555 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072048.pdf [firstpage_image] =>[orig_patent_app_number] => 12453037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453037
Semiconductor apparatus Apr 27, 2009 Issued
Array ( [id] => 5477721 [patent_doc_number] => 20090200678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/385621 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4484 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20090200678.pdf [firstpage_image] =>[orig_patent_app_number] => 12385621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385621
Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same Apr 13, 2009 Issued
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