
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5407397
[patent_doc_number] => 20090121295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES'
[patent_app_type] => utility
[patent_app_number] => 11/937637
[patent_app_country] => US
[patent_app_date] => 2007-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4522
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20090121295.pdf
[firstpage_image] =>[orig_patent_app_number] => 11937637
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/937637 | Method and structure for reducing induced mechanical stresses | Nov 8, 2007 | Issued |
Array
(
[id] => 196511
[patent_doc_number] => 07638349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Substrate preparation method for a MEMS fabrication process'
[patent_app_type] => utility
[patent_app_number] => 11/936060
[patent_app_country] => US
[patent_app_date] => 2007-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 54
[patent_no_of_words] => 11337
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/638/07638349.pdf
[firstpage_image] =>[orig_patent_app_number] => 11936060
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/936060 | Substrate preparation method for a MEMS fabrication process | Nov 5, 2007 | Issued |
Array
(
[id] => 4704702
[patent_doc_number] => 20080064226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'Method of processing a substrate, heating apparatus, and method of forming a pattern'
[patent_app_type] => utility
[patent_app_number] => 11/976499
[patent_app_country] => US
[patent_app_date] => 2007-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9670
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20080064226.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976499 | Method of processing a substrate, heating apparatus, and method of forming a pattern | Oct 24, 2007 | Abandoned |
Array
(
[id] => 345048
[patent_doc_number] => 07498235
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates'
[patent_app_type] => utility
[patent_app_number] => 11/924207
[patent_app_country] => US
[patent_app_date] => 2007-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 6612
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/498/07498235.pdf
[firstpage_image] =>[orig_patent_app_number] => 11924207
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/924207 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates | Oct 24, 2007 | Issued |
Array
(
[id] => 170540
[patent_doc_number] => 07662680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Method of producing a semiconductor element in a substrate and a semiconductor element'
[patent_app_type] => utility
[patent_app_number] => 11/864517
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 35
[patent_no_of_words] => 12637
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/662/07662680.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864517
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864517 | Method of producing a semiconductor element in a substrate and a semiconductor element | Sep 27, 2007 | Issued |
Array
(
[id] => 5425777
[patent_doc_number] => 20090085087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/863734
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3377
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20090085087.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863734
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863734 | Liner for tungsten/silicon dioxide interface in memory | Sep 27, 2007 | Issued |
Array
(
[id] => 232722
[patent_doc_number] => 07598147
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-06
[patent_title] => 'Method of forming CMOS with Si:C source/drain by laser melting and recrystallization'
[patent_app_type] => utility
[patent_app_number] => 11/860127
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6099
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/598/07598147.pdf
[firstpage_image] =>[orig_patent_app_number] => 11860127
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/860127 | Method of forming CMOS with Si:C source/drain by laser melting and recrystallization | Sep 23, 2007 | Issued |
Array
(
[id] => 159199
[patent_doc_number] => 07674689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-09
[patent_title] => 'Method of making an integrated circuit including singulating a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 11/858437
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 4557
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/674/07674689.pdf
[firstpage_image] =>[orig_patent_app_number] => 11858437
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/858437 | Method of making an integrated circuit including singulating a semiconductor wafer | Sep 19, 2007 | Issued |
Array
(
[id] => 4771988
[patent_doc_number] => 20080057646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Nonvolatile memory device and methods of fabricating and driving the same'
[patent_app_type] => utility
[patent_app_number] => 11/897370
[patent_app_country] => US
[patent_app_date] => 2007-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5317
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20080057646.pdf
[firstpage_image] =>[orig_patent_app_number] => 11897370
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/897370 | Nonvolatile memory device and methods of fabricating and driving the same | Aug 28, 2007 | Issued |
Array
(
[id] => 876001
[patent_doc_number] => 07358100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-15
[patent_title] => 'Bottom conductor for integrated MRAM'
[patent_app_type] => utility
[patent_app_number] => 11/891923
[patent_app_country] => US
[patent_app_date] => 2007-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1650
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/358/07358100.pdf
[firstpage_image] =>[orig_patent_app_number] => 11891923
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/891923 | Bottom conductor for integrated MRAM | Aug 13, 2007 | Issued |
Array
(
[id] => 4731170
[patent_doc_number] => 20080048233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'METHODS FOR MANUFACTURING A FINFET USING A CONVENTIONAL WAFER AND APPARATUS MANUFACTURED THEREFROM'
[patent_app_type] => utility
[patent_app_number] => 11/835182
[patent_app_country] => US
[patent_app_date] => 2007-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5604
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20080048233.pdf
[firstpage_image] =>[orig_patent_app_number] => 11835182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835182 | Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom | Aug 6, 2007 | Issued |
Array
(
[id] => 579399
[patent_doc_number] => 07452806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Method of forming inductor in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/882047
[patent_app_country] => US
[patent_app_date] => 2007-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3239
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/452/07452806.pdf
[firstpage_image] =>[orig_patent_app_number] => 11882047
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/882047 | Method of forming inductor in semiconductor device | Jul 29, 2007 | Issued |
Array
(
[id] => 373310
[patent_doc_number] => 07473613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-06
[patent_title] => 'Terraced film stack'
[patent_app_type] => utility
[patent_app_number] => 11/757594
[patent_app_country] => US
[patent_app_date] => 2007-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 4938
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/473/07473613.pdf
[firstpage_image] =>[orig_patent_app_number] => 11757594
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757594 | Terraced film stack | Jun 3, 2007 | Issued |
Array
(
[id] => 5129066
[patent_doc_number] => 20070205463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-06
[patent_title] => 'SEMICONDUCTOR-ON-INSULATOR SILICON WAFER'
[patent_app_type] => utility
[patent_app_number] => 11/745678
[patent_app_country] => US
[patent_app_date] => 2007-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3423
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20070205463.pdf
[firstpage_image] =>[orig_patent_app_number] => 11745678
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745678 | Semiconductor-on-insulator silicon wafer | May 7, 2007 | Issued |
Array
(
[id] => 5245133
[patent_doc_number] => 20070241367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Ultra Scalable High Speed Heterojunction Vertical n-Channel Misfets and Methods Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/735711
[patent_app_country] => US
[patent_app_date] => 2007-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4300
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20070241367.pdf
[firstpage_image] =>[orig_patent_app_number] => 11735711
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735711 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | Apr 15, 2007 | Issued |
Array
(
[id] => 5043802
[patent_doc_number] => 20070262473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION'
[patent_app_type] => utility
[patent_app_number] => 11/735397
[patent_app_country] => US
[patent_app_date] => 2007-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4487
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20070262473.pdf
[firstpage_image] =>[orig_patent_app_number] => 11735397
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735397 | Integrated circuit package system with contoured encapsulation | Apr 12, 2007 | Issued |
Array
(
[id] => 5110437
[patent_doc_number] => 20070194352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-23
[patent_title] => 'CMOS image sensor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/786169
[patent_app_country] => US
[patent_app_date] => 2007-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5644
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20070194352.pdf
[firstpage_image] =>[orig_patent_app_number] => 11786169
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/786169 | CMOS image sensor and method for manufacturing the same | Apr 9, 2007 | Issued |
Array
(
[id] => 813661
[patent_doc_number] => 07413933
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor'
[patent_app_type] => utility
[patent_app_number] => 11/697779
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2395
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/413/07413933.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697779
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697779 | Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor | Apr 8, 2007 | Issued |
Array
(
[id] => 558888
[patent_doc_number] => 07468533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-23
[patent_title] => 'Terraced film stack'
[patent_app_type] => utility
[patent_app_number] => 11/691770
[patent_app_country] => US
[patent_app_date] => 2007-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 4939
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/468/07468533.pdf
[firstpage_image] =>[orig_patent_app_number] => 11691770
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/691770 | Terraced film stack | Mar 26, 2007 | Issued |
Array
(
[id] => 5256759
[patent_doc_number] => 20070210391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'Dynamic Array Architecture'
[patent_app_type] => utility
[patent_app_number] => 11/683402
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 12299
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20070210391.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683402
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683402 | Dynamic array architecture | Mar 6, 2007 | Issued |