Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 185634 [patent_doc_number] => 07649198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Nano-array and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/509660 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 2944 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649198.pdf [firstpage_image] =>[orig_patent_app_number] => 11509660 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509660
Nano-array and fabrication method thereof Aug 24, 2006 Issued
Array ( [id] => 5145567 [patent_doc_number] => 20070045621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/510420 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 23046 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045621.pdf [firstpage_image] =>[orig_patent_app_number] => 11510420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510420
Semiconductor device and manufacturing method thereof Aug 24, 2006 Issued
Array ( [id] => 578707 [patent_doc_number] => 07452745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Photodetecting device' [patent_app_type] => utility [patent_app_number] => 11/510870 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 29 [patent_no_of_words] => 5229 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452745.pdf [firstpage_image] =>[orig_patent_app_number] => 11510870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510870
Photodetecting device Aug 23, 2006 Issued
Array ( [id] => 4733895 [patent_doc_number] => 20080050874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Metal-insulator-metal capacitor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/508890 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050874.pdf [firstpage_image] =>[orig_patent_app_number] => 11508890 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/508890
Metal-insulator-metal capacitor and method of manufacturing the same Aug 23, 2006 Issued
Array ( [id] => 408140 [patent_doc_number] => 07285457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Heterojunction bipolar transistor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/507008 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3071 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285457.pdf [firstpage_image] =>[orig_patent_app_number] => 11507008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507008
Heterojunction bipolar transistor and manufacturing method thereof Aug 20, 2006 Issued
Array ( [id] => 583241 [patent_doc_number] => 07445980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method and apparatus for improving stability of a 6T CMOS SRAM cell' [patent_app_type] => utility [patent_app_number] => 11/508009 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5075 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445980.pdf [firstpage_image] =>[orig_patent_app_number] => 11508009 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/508009
Method and apparatus for improving stability of a 6T CMOS SRAM cell Aug 20, 2006 Issued
Array ( [id] => 4999890 [patent_doc_number] => 20070042524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'MEMS devices having support structures with substantially vertical sidewalls and methods for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/506600 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13624 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042524.pdf [firstpage_image] =>[orig_patent_app_number] => 11506600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506600
MEMS devices having support structures with substantially vertical sidewalls and methods for fabricating the same Aug 17, 2006 Issued
Array ( [id] => 4988717 [patent_doc_number] => 20070155056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Silicon direct bonding method' [patent_app_type] => utility [patent_app_number] => 11/505420 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3534 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155056.pdf [firstpage_image] =>[orig_patent_app_number] => 11505420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505420
Silicon direct bonding method Aug 16, 2006 Issued
Array ( [id] => 7691977 [patent_doc_number] => 20070232056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/504680 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 5322 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232056.pdf [firstpage_image] =>[orig_patent_app_number] => 11504680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504680
Semiconductor device and method for manufacturing the same Aug 15, 2006 Abandoned
Array ( [id] => 5154478 [patent_doc_number] => 20070037361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method for forming void-free trench isolation layer' [patent_app_type] => utility [patent_app_number] => 11/504560 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037361.pdf [firstpage_image] =>[orig_patent_app_number] => 11504560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504560
Method for forming void-free trench isolation layer Aug 13, 2006 Issued
Array ( [id] => 33536 [patent_doc_number] => 07791071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Profiling solid state samples' [patent_app_type] => utility [patent_app_number] => 11/503680 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4443 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791071.pdf [firstpage_image] =>[orig_patent_app_number] => 11503680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503680
Profiling solid state samples Aug 13, 2006 Issued
Array ( [id] => 4651615 [patent_doc_number] => 20080038871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Multipath soldered thermal interface between a chip and its heat sink' [patent_app_type] => utility [patent_app_number] => 11/502380 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4652 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038871.pdf [firstpage_image] =>[orig_patent_app_number] => 11502380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502380
Multipath soldered thermal interface between a chip and its heat sink Aug 9, 2006 Abandoned
Array ( [id] => 5154468 [patent_doc_number] => 20070037351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method of fabricating a resistance based memory device and the memory device' [patent_app_type] => utility [patent_app_number] => 11/501880 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037351.pdf [firstpage_image] =>[orig_patent_app_number] => 11501880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501880
Method of fabricating a resistance based memory device and the memory device Aug 9, 2006 Issued
Array ( [id] => 373324 [patent_doc_number] => 07473627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Semiconducting device having a structure to improve contact processing margin, and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/502060 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2290 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473627.pdf [firstpage_image] =>[orig_patent_app_number] => 11502060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502060
Semiconducting device having a structure to improve contact processing margin, and method of fabricating the same Aug 8, 2006 Issued
Array ( [id] => 5031644 [patent_doc_number] => 20070096183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/500940 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9736 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096183.pdf [firstpage_image] =>[orig_patent_app_number] => 11500940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500940
Semiconductor device and method for fabricating the same Aug 8, 2006 Abandoned
Array ( [id] => 4688326 [patent_doc_number] => 20080032507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Method of treating a mask layer prior to performing an etching process' [patent_app_type] => utility [patent_app_number] => 11/499680 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9156 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032507.pdf [firstpage_image] =>[orig_patent_app_number] => 11499680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499680
Method of treating a mask layer prior to performing an etching process Aug 6, 2006 Issued
Array ( [id] => 4688303 [patent_doc_number] => 20080032484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Substrate bonding process with integrated vents' [patent_app_type] => utility [patent_app_number] => 11/499080 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032484.pdf [firstpage_image] =>[orig_patent_app_number] => 11499080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499080
Substrate bonding process with integrated vents Aug 3, 2006 Abandoned
Array ( [id] => 435827 [patent_doc_number] => 07262082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-28 [patent_title] => 'Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture' [patent_app_type] => utility [patent_app_number] => 11/498614 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 208 [patent_no_of_words] => 45613 [patent_no_of_claims] => 200 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 455 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262082.pdf [firstpage_image] =>[orig_patent_app_number] => 11498614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498614
Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture Aug 2, 2006 Issued
Array ( [id] => 602433 [patent_doc_number] => 07432196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/498079 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 47 [patent_no_of_words] => 17489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432196.pdf [firstpage_image] =>[orig_patent_app_number] => 11498079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498079
Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device Aug 2, 2006 Issued
Array ( [id] => 7692100 [patent_doc_number] => 20070231933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Using reverse arrangement for trend test in statistical process control for manufacture of semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/498970 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8058 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20070231933.pdf [firstpage_image] =>[orig_patent_app_number] => 11498970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498970
Using reverse arrangement for trend test in statistical process control for manufacture of semiconductor integrated circuits Aug 1, 2006 Issued
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