Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4985914 [patent_doc_number] => 20070152252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Reducing aluminum dissolution in high pH solutions' [patent_app_type] => utility [patent_app_number] => 11/322885 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4879 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152252.pdf [firstpage_image] =>[orig_patent_app_number] => 11322885 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322885
Reducing aluminum dissolution in high pH solutions Dec 29, 2005 Abandoned
Array ( [id] => 326565 [patent_doc_number] => 07514336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Robust shallow trench isolation structures and a method for forming shallow trench isolation structures' [patent_app_type] => utility [patent_app_number] => 11/321206 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2610 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514336.pdf [firstpage_image] =>[orig_patent_app_number] => 11321206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321206
Robust shallow trench isolation structures and a method for forming shallow trench isolation structures Dec 28, 2005 Issued
Array ( [id] => 5141929 [patent_doc_number] => 20070004145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length' [patent_app_type] => utility [patent_app_number] => 11/318960 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004145.pdf [firstpage_image] =>[orig_patent_app_number] => 11318960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318960
Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length Dec 26, 2005 Issued
Array ( [id] => 5694321 [patent_doc_number] => 20060154468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Manufacturing method of semiconductor device, semiconductor device, circuit board, electro-optic device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/311800 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10065 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154468.pdf [firstpage_image] =>[orig_patent_app_number] => 11311800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311800
Manufacturing method of semiconductor device, semiconductor device, circuit board, electro-optic device, and electronic apparatus Dec 18, 2005 Issued
Array ( [id] => 4997628 [patent_doc_number] => 20070040262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Flexible substrate capable of preventing lead thereon from fracturing' [patent_app_type] => utility [patent_app_number] => 11/303184 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 995 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040262.pdf [firstpage_image] =>[orig_patent_app_number] => 11303184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303184
Flexible substrate capable of preventing lead thereon from fracturing Dec 14, 2005 Abandoned
Array ( [id] => 504748 [patent_doc_number] => 07202140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Method to fabricate Ge and Si devices together for performance enhancement' [patent_app_type] => utility [patent_app_number] => 11/297540 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202140.pdf [firstpage_image] =>[orig_patent_app_number] => 11297540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297540
Method to fabricate Ge and Si devices together for performance enhancement Dec 6, 2005 Issued
Array ( [id] => 239930 [patent_doc_number] => 07592648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method' [patent_app_type] => utility [patent_app_number] => 11/295706 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5160 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592648.pdf [firstpage_image] =>[orig_patent_app_number] => 11295706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295706
Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method Dec 5, 2005 Issued
Array ( [id] => 579137 [patent_doc_number] => 07452783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Capacitor for a semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/286316 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7367 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452783.pdf [firstpage_image] =>[orig_patent_app_number] => 11286316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286316
Capacitor for a semiconductor device and method of forming the same Nov 22, 2005 Issued
Array ( [id] => 5843602 [patent_doc_number] => 20060121687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Semiconductor device having a multi-bridge-channel and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/285300 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20060121687.pdf [firstpage_image] =>[orig_patent_app_number] => 11285300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285300
Semiconductor device having a multi-bridge-channel and method for fabricating the same Nov 22, 2005 Issued
Array ( [id] => 588914 [patent_doc_number] => 07435612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'CMOS-MEMS process' [patent_app_type] => utility [patent_app_number] => 11/270523 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 1807 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435612.pdf [firstpage_image] =>[orig_patent_app_number] => 11270523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270523
CMOS-MEMS process Nov 9, 2005 Issued
Array ( [id] => 5823780 [patent_doc_number] => 20060060962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Electronic package having a folded package substrate' [patent_app_type] => utility [patent_app_number] => 11/270936 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2287 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060962.pdf [firstpage_image] =>[orig_patent_app_number] => 11270936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270936
Electronic package having a folded package substrate Nov 9, 2005 Issued
Array ( [id] => 830136 [patent_doc_number] => 07399690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Methods of fabricating semiconductor devices and structures thereof' [patent_app_type] => utility [patent_app_number] => 11/268924 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/399/07399690.pdf [firstpage_image] =>[orig_patent_app_number] => 11268924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268924
Methods of fabricating semiconductor devices and structures thereof Nov 7, 2005 Issued
Array ( [id] => 246950 [patent_doc_number] => 07585702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-08 [patent_title] => 'Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate' [patent_app_type] => utility [patent_app_number] => 11/270676 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7718 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/585/07585702.pdf [firstpage_image] =>[orig_patent_app_number] => 11270676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270676
Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate Nov 7, 2005 Issued
Array ( [id] => 5863180 [patent_doc_number] => 20060097310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Non-volatile memory devices including divided charge storage structures and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/268034 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7629 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097310.pdf [firstpage_image] =>[orig_patent_app_number] => 11268034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268034
Methods of fabricating non-volatile memory devices including divided charge storage structures Nov 6, 2005 Issued
Array ( [id] => 5865630 [patent_doc_number] => 20060099760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Storage capacitors for semiconductor devices and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/266520 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6433 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099760.pdf [firstpage_image] =>[orig_patent_app_number] => 11266520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266520
Methods of forming storage capacitors for semiconductor devices Nov 2, 2005 Issued
Array ( [id] => 5590988 [patent_doc_number] => 20060040440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'NAND FLASH MEMORY CELL ROW AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/163818 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3718 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040440.pdf [firstpage_image] =>[orig_patent_app_number] => 11163818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163818
NAND flash memory cell row and manufacturing method thereof Oct 30, 2005 Issued
Array ( [id] => 675813 [patent_doc_number] => 07087526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method of fabricating a p-type CaO-doped SrCu2O2 thin film' [patent_app_type] => utility [patent_app_number] => 11/261020 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1712 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087526.pdf [firstpage_image] =>[orig_patent_app_number] => 11261020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261020
Method of fabricating a p-type CaO-doped SrCu2O2 thin film Oct 26, 2005 Issued
Array ( [id] => 5805128 [patent_doc_number] => 20060091481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/259473 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091481.pdf [firstpage_image] =>[orig_patent_app_number] => 11259473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259473
Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same Oct 25, 2005 Issued
Array ( [id] => 465385 [patent_doc_number] => 07239030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Flexible wiring board for tape carrier package having improved flame resistance' [patent_app_type] => utility [patent_app_number] => 11/258940 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 13046 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239030.pdf [firstpage_image] =>[orig_patent_app_number] => 11258940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258940
Flexible wiring board for tape carrier package having improved flame resistance Oct 25, 2005 Issued
Array ( [id] => 5040795 [patent_doc_number] => 20070093077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Method of forming a trench semiconductor device and structure therefor' [patent_app_type] => utility [patent_app_number] => 11/256409 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093077.pdf [firstpage_image] =>[orig_patent_app_number] => 11256409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256409
Method of forming a trench semiconductor device and structure therefor Oct 23, 2005 Issued
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