Patrick Hamo

Array ( [id] => 658077 [patent_doc_number] => 07105381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Wafer alignment method' [patent_app_type] => utility [patent_app_number] => 11/167960 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2588 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105381.pdf [firstpage_image] =>[orig_patent_app_number] => 11167960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 810144 [patent_doc_number] => 07416994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Atomic layer deposition systems and methods including metal beta-diketiminate compounds' [patent_app_type] => utility [patent_app_number] => 11/168160 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9497 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/416/07416994.pdf [firstpage_image] =>[orig_patent_app_number] => 11168160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6924595 [patent_doc_number] => 20050237850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Method and apparatus for improving stability of a 6T CMOS SRAM cell' [patent_app_type] => utility [patent_app_number] => 11/165724 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5039 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20050237850.pdf [firstpage_image] =>[orig_patent_app_number] => 11165724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 521365 [patent_doc_number] => 07186591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Method of encapsulating an assembly with a low temperature silicone rubber compound' [patent_app_type] => utility [patent_app_number] => 11/165230 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186591.pdf [firstpage_image] =>[orig_patent_app_number] => 11165230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6978020 [patent_doc_number] => 20050287738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/159130 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6350 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287738.pdf [firstpage_image] =>[orig_patent_app_number] => 11159130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 578761 [patent_doc_number] => 07452748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-18 [patent_title] => 'Strap assembly comprising functional block deposited therein and method of making same' [patent_app_type] => utility [patent_app_number] => 11/159550 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 48 [patent_no_of_words] => 21210 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452748.pdf [firstpage_image] =>[orig_patent_app_number] => 11159550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5710541 [patent_doc_number] => 20060051886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Liquid crystal display device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/158000 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6957 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20060051886.pdf [firstpage_image] =>[orig_patent_app_number] => 11158000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5688433 [patent_doc_number] => 20060286748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Terraced film stack' [patent_app_type] => utility [patent_app_number] => 11/158220 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4906 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286748.pdf [firstpage_image] =>[orig_patent_app_number] => 11158220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5177649 [patent_doc_number] => 20070178709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Method of forming nanowires with a narrow diameter distribution' [patent_app_type] => utility [patent_app_number] => 11/158760 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3464 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20070178709.pdf [firstpage_image] =>[orig_patent_app_number] => 11158760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5688414 [patent_doc_number] => 20060286729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate' [patent_app_type] => utility [patent_app_number] => 11/159430 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286729.pdf [firstpage_image] =>[orig_patent_app_number] => 11159430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 352943 [patent_doc_number] => 07491966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Semiconductor substrate and process for producing it' [patent_app_type] => utility [patent_app_number] => 11/157260 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4087 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491966.pdf [firstpage_image] =>[orig_patent_app_number] => 11157260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5895003 [patent_doc_number] => 20060003542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method of oxidizing object to be processed and oxidation system' [patent_app_type] => utility [patent_app_number] => 11/157170 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5355 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003542.pdf [firstpage_image] =>[orig_patent_app_number] => 11157170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6965110 [patent_doc_number] => 20050232007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Flash EEPROM with function bit by bit erasing' [patent_app_type] => utility [patent_app_number] => 11/156392 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20050232007.pdf [firstpage_image] =>[orig_patent_app_number] => 11156392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 885735 [patent_doc_number] => 07352019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Capacitance reduction by tunnel formation for use with a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/156160 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352019.pdf [firstpage_image] =>[orig_patent_app_number] => 11156160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7056093 [patent_doc_number] => 20050277268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Manufacturing method of semiconductor wafer having lid part and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/152950 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9135 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20050277268.pdf [firstpage_image] =>[orig_patent_app_number] => 11152950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 552793 [patent_doc_number] => 07160751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Method of making a SOI silicon structure' [patent_app_type] => utility [patent_app_number] => 11/151680 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 1489 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/160/07160751.pdf [firstpage_image] =>[orig_patent_app_number] => 11151680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6929044 [patent_doc_number] => 20050280077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Triple-diffused trench MOSFET' [patent_app_type] => utility [patent_app_number] => 11/150016 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3241 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20050280077.pdf [firstpage_image] =>[orig_patent_app_number] => 11150016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5785589 [patent_doc_number] => 20060205150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'METHOD OF FABRICATING FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/160091 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2874 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205150.pdf [firstpage_image] =>[orig_patent_app_number] => 11160091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 589324 [patent_doc_number] => 07435658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method of manufacturing metal-oxide-semiconductor transistor' [patent_app_type] => utility [patent_app_number] => 11/147506 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4144 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435658.pdf [firstpage_image] =>[orig_patent_app_number] => 11147506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 675709 [patent_doc_number] => 07087462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method for forming leadless semiconductor packages' [patent_app_type] => utility [patent_app_number] => 11/160070 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3463 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087462.pdf [firstpage_image] =>[orig_patent_app_number] => 11160070 [rel_patent_id] =>[rel_patent_doc_number] =>)