
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 766293
[patent_doc_number] => 07008853
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-03-07
[patent_title] => 'Method and system for fabricating free-standing nanostructures'
[patent_app_type] => utility
[patent_app_number] => 11/066320
[patent_app_country] => US
[patent_app_date] => 2005-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 5117
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/008/07008853.pdf
[firstpage_image] =>[orig_patent_app_number] => 11066320
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/066320 | Method and system for fabricating free-standing nanostructures | Feb 24, 2005 | Issued |
Array
(
[id] => 7161995
[patent_doc_number] => 20050199903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Semiconductor device having quantum well structure, and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/057830
[patent_app_country] => US
[patent_app_date] => 2005-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12193
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20050199903.pdf
[firstpage_image] =>[orig_patent_app_number] => 11057830
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/057830 | Semiconductor device having quantum well structure, and method of forming the same | Feb 14, 2005 | Issued |
Array
(
[id] => 7050905
[patent_doc_number] => 20050186792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Manufacturing method of a semiconductor device with a metal gate electrode and a structure thereof'
[patent_app_type] => utility
[patent_app_number] => 11/055770
[patent_app_country] => US
[patent_app_date] => 2005-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6147
[patent_no_of_claims] => 23
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20050186792.pdf
[firstpage_image] =>[orig_patent_app_number] => 11055770
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055770 | Manufacturing method of a semiconductor device with a metal gate electrode and a structure thereof | Feb 10, 2005 | Issued |
Array
(
[id] => 7005334
[patent_doc_number] => 20050170647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby'
[patent_app_type] => utility
[patent_app_number] => 11/055940
[patent_app_country] => US
[patent_app_date] => 2005-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 9264
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 0
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20050170647.pdf
[firstpage_image] =>[orig_patent_app_number] => 11055940
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055940 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Feb 9, 2005 | Abandoned |
Array
(
[id] => 7180146
[patent_doc_number] => 20050190605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Semiconductor memory and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/053952
[patent_app_country] => US
[patent_app_date] => 2005-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
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[patent_no_of_words] => 14309
[patent_no_of_claims] => 22
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[pdf_file] => publications/A1/0190/20050190605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11053952
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/053952 | Semiconductor memory and method of manufacturing the same | Feb 9, 2005 | Issued |
Array
(
[id] => 485604
[patent_doc_number] => 07217636
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-15
[patent_title] => 'Semiconductor-on-insulator silicon wafer'
[patent_app_type] => utility
[patent_app_number] => 11/054579
[patent_app_country] => US
[patent_app_date] => 2005-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3394
[patent_no_of_claims] => 11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217636.pdf
[firstpage_image] =>[orig_patent_app_number] => 11054579
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/054579 | Semiconductor-on-insulator silicon wafer | Feb 8, 2005 | Issued |
Array
(
[id] => 931132
[patent_doc_number] => 06979636
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Method for forming heightened solder bumps on circuit boards'
[patent_app_type] => utility
[patent_app_number] => 11/052890
[patent_app_country] => US
[patent_app_date] => 2005-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 1763
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/979/06979636.pdf
[firstpage_image] =>[orig_patent_app_number] => 11052890
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/052890 | Method for forming heightened solder bumps on circuit boards | Feb 8, 2005 | Issued |
Array
(
[id] => 7162279
[patent_doc_number] => 20050200027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Conductive through wafer vias'
[patent_app_type] => utility
[patent_app_number] => 11/052181
[patent_app_country] => US
[patent_app_date] => 2005-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3947
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 23
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20050200027.pdf
[firstpage_image] =>[orig_patent_app_number] => 11052181
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/052181 | Conductive through wafer vias | Feb 6, 2005 | Abandoned |
Array
(
[id] => 515085
[patent_doc_number] => 07192864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Method of forming interconnection lines for semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/049730
[patent_app_country] => US
[patent_app_date] => 2005-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2789
[patent_no_of_claims] => 16
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[patent_words_short_claim] => 192
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/192/07192864.pdf
[firstpage_image] =>[orig_patent_app_number] => 11049730
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/049730 | Method of forming interconnection lines for semiconductor device | Feb 3, 2005 | Issued |
Array
(
[id] => 7047408
[patent_doc_number] => 20050183295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Manufacturing method and manufacturing apparatus for semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/048780
[patent_app_country] => US
[patent_app_date] => 2005-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5121
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20050183295.pdf
[firstpage_image] =>[orig_patent_app_number] => 11048780
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/048780 | Manufacturing method and manufacturing apparatus for semiconductor device | Feb 2, 2005 | Issued |
Array
(
[id] => 658064
[patent_doc_number] => 07105374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-09-12
[patent_title] => 'Memory cell containing copolymer containing diarylacetylene portion'
[patent_app_type] => utility
[patent_app_number] => 11/033941
[patent_app_country] => US
[patent_app_date] => 2005-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 7372
[patent_no_of_claims] => 24
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105374.pdf
[firstpage_image] =>[orig_patent_app_number] => 11033941
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/033941 | Memory cell containing copolymer containing diarylacetylene portion | Jan 11, 2005 | Issued |
Array
(
[id] => 587583
[patent_doc_number] => 07439194
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'Lanthanide doped TiOx dielectric films by plasma oxidation'
[patent_app_type] => utility
[patent_app_number] => 11/031289
[patent_app_country] => US
[patent_app_date] => 2005-01-07
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[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/07/439/07439194.pdf
[firstpage_image] =>[orig_patent_app_number] => 11031289
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/031289 | Lanthanide doped TiOx dielectric films by plasma oxidation | Jan 6, 2005 | Issued |
Array
(
[id] => 7178854
[patent_doc_number] => 20050124145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Mask for sequential lateral solidification and crystallization method using thereof'
[patent_app_type] => utility
[patent_app_number] => 11/029395
[patent_app_country] => US
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[pdf_file] => publications/A1/0124/20050124145.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029395
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029395 | Mask for sequential lateral solidification and crystallization method using thereof | Jan 5, 2005 | Issued |
Array
(
[id] => 7143580
[patent_doc_number] => 20050118535
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[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Method of processing a substrate, heating apparatus, and method of forming a pattern'
[patent_app_type] => utility
[patent_app_number] => 11/029375
[patent_app_country] => US
[patent_app_date] => 2005-01-06
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[pdf_file] => publications/A1/0118/20050118535.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029375
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029375 | Method of processing a substrate, heating apparatus, and method of forming a pattern | Jan 5, 2005 | Issued |
Array
(
[id] => 5631759
[patent_doc_number] => 20060148229
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[patent_title] => 'Phase change memory device and method of manufacturing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028841 | Phase change memory device and method of manufacturing | Jan 3, 2005 | Issued |
Array
(
[id] => 496804
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[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Methods of fabricating ferroelectric memory devices having expanded plate lines'
[patent_app_type] => utility
[patent_app_number] => 11/029232
[patent_app_country] => US
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[pdf_file] => patents/07/208/07208367.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029232
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029232 | Methods of fabricating ferroelectric memory devices having expanded plate lines | Jan 3, 2005 | Issued |
Array
(
[id] => 7253769
[patent_doc_number] => 20050142846
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[patent_issue_date] => 2005-06-30
[patent_title] => 'Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures'
[patent_app_type] => utility
[patent_app_number] => 11/029220
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[firstpage_image] =>[orig_patent_app_number] => 11029220
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029220 | Method and apparatus for maintaining parallelism of layers and/or achieving desired thicknesses of layers during the electrochemical fabrication of structures | Jan 2, 2005 | Issued |
Array
(
[id] => 6963811
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[patent_title] => 'Sensor with at least one micromechanical structure, and method for producing it'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028370 | Sensor with at least one micromechanical structure, and method for producing it | Jan 2, 2005 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 11024610
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024610 | Manufacturing method of semiconductor device | Dec 29, 2004 | Issued |
Array
(
[id] => 7253070
[patent_doc_number] => 20050142681
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[patent_title] => 'Mask and method of manufacturing liquid crystal display device using the same'
[patent_app_type] => utility
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[pdf_file] => publications/A1/0142/20050142681.pdf
[firstpage_image] =>[orig_patent_app_number] => 11022650
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022650 | Mask and method of manufacturing liquid crystal display device using the same | Dec 27, 2004 | Issued |