
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7253359
[patent_doc_number] => 20050142748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Nonvolatile memory device and methods of fabricating and driving the same'
[patent_app_type] => utility
[patent_app_number] => 11/024210
[patent_app_country] => US
[patent_app_date] => 2004-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5205
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20050142748.pdf
[firstpage_image] =>[orig_patent_app_number] => 11024210
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024210 | Nonvolatile memory device and methods of fabricating and driving the same | Dec 26, 2004 | Issued |
Array
(
[id] => 5656026
[patent_doc_number] => 20060141762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Interlocking via for package via integrity'
[patent_app_type] => utility
[patent_app_number] => 11/023750
[patent_app_country] => US
[patent_app_date] => 2004-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5930
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141762.pdf
[firstpage_image] =>[orig_patent_app_number] => 11023750
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/023750 | Interlocking via for package via integrity | Dec 26, 2004 | Issued |
Array
(
[id] => 836898
[patent_doc_number] => 07393713
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-01
[patent_title] => 'Method of fabricating near field optical probe'
[patent_app_type] => utility
[patent_app_number] => 11/020180
[patent_app_country] => US
[patent_app_date] => 2004-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 3950
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/393/07393713.pdf
[firstpage_image] =>[orig_patent_app_number] => 11020180
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/020180 | Method of fabricating near field optical probe | Dec 26, 2004 | Issued |
Array
(
[id] => 7154342
[patent_doc_number] => 20050082584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Methods and apparatuses for producing a polymer memory device'
[patent_app_type] => utility
[patent_app_number] => 11/007113
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2616
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082584.pdf
[firstpage_image] =>[orig_patent_app_number] => 11007113
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/007113 | Methods and apparatuses for producing a polymer memory device | Dec 6, 2004 | Issued |
Array
(
[id] => 500188
[patent_doc_number] => 07205195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Method for fabricating NROM memory cells with trench transistors'
[patent_app_type] => utility
[patent_app_number] => 11/006049
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3548
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11006049
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/006049 | Method for fabricating NROM memory cells with trench transistors | Dec 6, 2004 | Issued |
Array
(
[id] => 679646
[patent_doc_number] => 07084020
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Manufacturing method of a thin-film semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/004858
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 38
[patent_no_of_words] => 6289
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/084/07084020.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004858
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004858 | Manufacturing method of a thin-film semiconductor device | Dec 6, 2004 | Issued |
Array
(
[id] => 887930
[patent_doc_number] => 07348237
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'NOR flash memory cell with high storage density'
[patent_app_type] => utility
[patent_app_number] => 11/005909
[patent_app_country] => US
[patent_app_date] => 2004-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 8293
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/348/07348237.pdf
[firstpage_image] =>[orig_patent_app_number] => 11005909
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/005909 | NOR flash memory cell with high storage density | Dec 5, 2004 | Issued |
Array
(
[id] => 5894991
[patent_doc_number] => 20060003530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Semiconductor memory device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/004420
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4464
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20060003530.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004420
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004420 | Semiconductor memory device and method for fabricating the same | Dec 2, 2004 | Issued |
Array
(
[id] => 782768
[patent_doc_number] => 06992016
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'Chemical processing method, and method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/000978
[patent_app_country] => US
[patent_app_date] => 2004-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6448
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/992/06992016.pdf
[firstpage_image] =>[orig_patent_app_number] => 11000978
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/000978 | Chemical processing method, and method of manufacturing semiconductor device | Dec 1, 2004 | Issued |
Array
(
[id] => 5865632
[patent_doc_number] => 20060099763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 10/904210
[patent_app_country] => US
[patent_app_date] => 2004-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2483
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20060099763.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904210
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904210 | METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICE | Oct 27, 2004 | Abandoned |
Array
(
[id] => 7154219
[patent_doc_number] => 20050082528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Liquid crystal display'
[patent_app_type] => utility
[patent_app_number] => 10/973619
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 69
[patent_figures_cnt] => 69
[patent_no_of_words] => 22753
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082528.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973619
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973619 | Liquid crystal display | Oct 26, 2004 | Issued |
Array
(
[id] => 707590
[patent_doc_number] => 07060550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Method of fabricating a bipolar junction transistor'
[patent_app_type] => utility
[patent_app_number] => 10/904150
[patent_app_country] => US
[patent_app_date] => 2004-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 1884
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/060/07060550.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904150
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904150 | Method of fabricating a bipolar junction transistor | Oct 25, 2004 | Issued |
Array
(
[id] => 634057
[patent_doc_number] => 07129113
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-31
[patent_title] => 'Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture'
[patent_app_type] => utility
[patent_app_number] => 10/971856
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 68
[patent_figures_cnt] => 206
[patent_no_of_words] => 45596
[patent_no_of_claims] => 200
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 458
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129113.pdf
[firstpage_image] =>[orig_patent_app_number] => 10971856
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/971856 | Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture | Oct 21, 2004 | Issued |
Array
(
[id] => 485479
[patent_doc_number] => 07217607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Method for manufacturing semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 10/968050
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 29
[patent_no_of_words] => 6808
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968050
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968050 | Method for manufacturing semiconductor integrated circuit device | Oct 19, 2004 | Issued |
Array
(
[id] => 6936595
[patent_doc_number] => 20050110156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Wafer level packages for chips with sawn edge protection'
[patent_app_type] => utility
[patent_app_number] => 10/967020
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3666
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20050110156.pdf
[firstpage_image] =>[orig_patent_app_number] => 10967020
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/967020 | Wafer level packages for chips with sawn edge protection | Oct 14, 2004 | Issued |
Array
(
[id] => 700242
[patent_doc_number] => 07067911
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-06-27
[patent_title] => 'Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture'
[patent_app_type] => utility
[patent_app_number] => 10/966816
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 68
[patent_figures_cnt] => 206
[patent_no_of_words] => 45559
[patent_no_of_claims] => 150
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 398
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067911.pdf
[firstpage_image] =>[orig_patent_app_number] => 10966816
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/966816 | Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture | Oct 14, 2004 | Issued |
Array
(
[id] => 690513
[patent_doc_number] => 07074695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-11
[patent_title] => 'DBG system and method with adhesive layer severing'
[patent_app_type] => utility
[patent_app_number] => 10/959713
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 16
[patent_no_of_words] => 2200
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/074/07074695.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959713
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959713 | DBG system and method with adhesive layer severing | Oct 5, 2004 | Issued |
Array
(
[id] => 662649
[patent_doc_number] => 07101750
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Semiconductor device for integrated injection logic cell and process for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/951320
[patent_app_country] => US
[patent_app_date] => 2004-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4338
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/101/07101750.pdf
[firstpage_image] =>[orig_patent_app_number] => 10951320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/951320 | Semiconductor device for integrated injection logic cell and process for fabricating the same | Sep 26, 2004 | Issued |
Array
(
[id] => 654547
[patent_doc_number] => 07109066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Method and device for forming spacer structures for packaging optical reflection devices'
[patent_app_type] => utility
[patent_app_number] => 10/947879
[patent_app_country] => US
[patent_app_date] => 2004-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3841
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/109/07109066.pdf
[firstpage_image] =>[orig_patent_app_number] => 10947879
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/947879 | Method and device for forming spacer structures for packaging optical reflection devices | Sep 21, 2004 | Issued |
Array
(
[id] => 5828314
[patent_doc_number] => 20060063338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Shallow trench isolation depth extension using oxygen implantation'
[patent_app_type] => utility
[patent_app_number] => 10/946030
[patent_app_country] => US
[patent_app_date] => 2004-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3576
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20060063338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10946030
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/946030 | Shallow trench isolation depth extension using oxygen implantation | Sep 19, 2004 | Abandoned |