
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7465360
[patent_doc_number] => 20040166621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Static NVRAM with ultra thin tunnel oxides'
[patent_app_type] => new
[patent_app_number] => 10/786726
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9373
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20040166621.pdf
[firstpage_image] =>[orig_patent_app_number] => 10786726
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/786726 | Static NVRAM with ultra thin tunnel oxides | Feb 24, 2004 | Issued |
Array
(
[id] => 7235589
[patent_doc_number] => 20040157449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Method for fabricating electrode device'
[patent_app_type] => new
[patent_app_number] => 10/772319
[patent_app_country] => US
[patent_app_date] => 2004-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2470
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20040157449.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772319
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772319 | Method for fabricating electrode device | Feb 5, 2004 | Abandoned |
Array
(
[id] => 757616
[patent_doc_number] => 07015086
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology'
[patent_app_type] => utility
[patent_app_number] => 10/772940
[patent_app_country] => US
[patent_app_date] => 2004-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 2983
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 436
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/015/07015086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772940
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772940 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Feb 4, 2004 | Issued |
Array
(
[id] => 7609847
[patent_doc_number] => 06998341
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Process for forming a diffusion barrier material nitride film'
[patent_app_type] => utility
[patent_app_number] => 10/771828
[patent_app_country] => US
[patent_app_date] => 2004-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 6015
[patent_no_of_claims] => 19
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/998/06998341.pdf
[firstpage_image] =>[orig_patent_app_number] => 10771828
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/771828 | Process for forming a diffusion barrier material nitride film | Feb 3, 2004 | Issued |
Array
(
[id] => 7005326
[patent_doc_number] => 20050170639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Forming a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/769127
[patent_app_country] => US
[patent_app_date] => 2004-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3273
[patent_no_of_claims] => 30
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[pdf_file] => publications/A1/0170/20050170639.pdf
[firstpage_image] =>[orig_patent_app_number] => 10769127
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/769127 | Forming a semiconductor device | Jan 29, 2004 | Issued |
Array
(
[id] => 7429378
[patent_doc_number] => 20040209464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Plating method and plating apparatus'
[patent_app_type] => new
[patent_app_number] => 10/484630
[patent_app_country] => US
[patent_app_date] => 2004-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7015
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 152
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20040209464.pdf
[firstpage_image] =>[orig_patent_app_number] => 10484630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484630 | Plating method and plating apparatus | Jan 22, 2004 | Abandoned |
Array
(
[id] => 512337
[patent_doc_number] => 07199433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-03
[patent_title] => 'Method of manufacturing semiconductor integrated circuit device having capacitor element'
[patent_app_type] => utility
[patent_app_number] => 10/756305
[patent_app_country] => US
[patent_app_date] => 2004-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 71
[patent_no_of_words] => 19069
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/199/07199433.pdf
[firstpage_image] =>[orig_patent_app_number] => 10756305
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/756305 | Method of manufacturing semiconductor integrated circuit device having capacitor element | Jan 13, 2004 | Issued |
Array
(
[id] => 869653
[patent_doc_number] => 07365414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-29
[patent_title] => 'Component packaging apparatus, systems, and methods'
[patent_app_type] => utility
[patent_app_number] => 10/750459
[patent_app_country] => US
[patent_app_date] => 2003-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 6006
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/365/07365414.pdf
[firstpage_image] =>[orig_patent_app_number] => 10750459
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/750459 | Component packaging apparatus, systems, and methods | Dec 30, 2003 | Issued |
Array
(
[id] => 7074843
[patent_doc_number] => 20050148111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Method and system for producing resilient solder joints'
[patent_app_type] => utility
[patent_app_number] => 10/748480
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2874
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20050148111.pdf
[firstpage_image] =>[orig_patent_app_number] => 10748480
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/748480 | Method and system for producing resilient solder joints | Dec 29, 2003 | Abandoned |
Array
(
[id] => 487418
[patent_doc_number] => 07217967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'CMOS image sensor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/746980
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5621
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217967.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746980 | CMOS image sensor and method for manufacturing the same | Dec 22, 2003 | Issued |
Array
(
[id] => 7359691
[patent_doc_number] => 20040216660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Method of forming high-quality quantum dots by using a strained layer'
[patent_app_type] => new
[patent_app_number] => 10/734543
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1999
[patent_no_of_claims] => 7
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20040216660.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734543 | Method of forming high-quality quantum dots by using a strained layer | Dec 11, 2003 | Abandoned |
Array
(
[id] => 7675100
[patent_doc_number] => 20040127018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Bit line contacts'
[patent_app_type] => new
[patent_app_number] => 10/734438
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5295
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20040127018.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734438 | Bit line contacts | Dec 10, 2003 | Issued |
Array
(
[id] => 990713
[patent_doc_number] => 06919239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-19
[patent_title] => 'Method for forming a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/726529
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/919/06919239.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726529
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726529 | Method for forming a semiconductor device | Dec 3, 2003 | Issued |
Array
(
[id] => 7178890
[patent_doc_number] => 20050124155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Electrode structures and method to form electrode structures that minimize electrode work function variation'
[patent_app_type] => utility
[patent_app_number] => 10/725500
[patent_app_country] => US
[patent_app_date] => 2003-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3177
[patent_no_of_claims] => 59
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20050124155.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725500 | Electrode structures and method to form electrode structures that minimize electrode work function variation | Dec 2, 2003 | Abandoned |
Array
(
[id] => 7383214
[patent_doc_number] => 20040082123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Semiconductor device and a method for forming patterns'
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[patent_app_country] => US
[patent_app_date] => 2003-12-03
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20040082123.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726831 | Semiconductor device and a method for forming patterns | Dec 2, 2003 | Issued |
Array
(
[id] => 7376048
[patent_doc_number] => 20040219801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Partially transparent photovoltaic modules'
[patent_app_type] => new
[patent_app_number] => 10/726179
[patent_app_country] => US
[patent_app_date] => 2003-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20040219801.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726179
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726179 | Partially transparent photovoltaic modules | Dec 1, 2003 | Abandoned |
Array
(
[id] => 7144272
[patent_doc_number] => 20050118803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Building metal pillars in a chip for structure support'
[patent_app_type] => utility
[patent_app_number] => 10/726140
[patent_app_country] => US
[patent_app_date] => 2003-12-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20050118803.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726140
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726140 | Building metal pillars in a chip for structure support | Dec 1, 2003 | Issued |
Array
(
[id] => 7061320
[patent_doc_number] => 20050003681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Siloxane-based resin and a semiconductor interlayer insulating film using the same'
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[pdf_file] => publications/A1/0003/20050003681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10722460
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/722460 | Siloxane-based resin and a semiconductor interlayer insulating film using the same | Nov 27, 2003 | Issued |
Array
(
[id] => 7408986
[patent_doc_number] => 20040106278
[patent_country] => US
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[patent_issue_date] => 2004-06-03
[patent_title] => 'Method of eliminating photoresist poisoning in damascene applications'
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[pdf_file] => publications/A1/0106/20040106278.pdf
[firstpage_image] =>[orig_patent_app_number] => 10718887
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718887 | Method of eliminating photoresist poisoning in damascene applications | Nov 20, 2003 | Issued |
Array
(
[id] => 948797
[patent_doc_number] => 06962833
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-08
[patent_title] => 'Magnetic shield for integrated circuit packaging'
[patent_app_type] => utility
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[patent_app_country] => US
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/962/06962833.pdf
[firstpage_image] =>[orig_patent_app_number] => 10719419
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/719419 | Magnetic shield for integrated circuit packaging | Nov 20, 2003 | Issued |