Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17373793 [patent_doc_number] => 20220028845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/476489 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476489
Display panel including bank structures Sep 15, 2021 Issued
Array ( [id] => 18447045 [patent_doc_number] => 11682621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Connector for implementing multi-faceted interconnection [patent_app_type] => utility [patent_app_number] => 17/463736 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5221 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463736
Connector for implementing multi-faceted interconnection Aug 31, 2021 Issued
Array ( [id] => 19046710 [patent_doc_number] => 11935830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Integrated circuit with frontside and backside conductive layers and exposed backside substrate [patent_app_type] => utility [patent_app_number] => 17/446515 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446515 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446515
Integrated circuit with frontside and backside conductive layers and exposed backside substrate Aug 30, 2021 Issued
Array ( [id] => 18222552 [patent_doc_number] => 20230061546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => STRUCTURE AND METHOD FOR MULTIPLE BEOL K-VALUE DIELECTRIC [patent_app_type] => utility [patent_app_number] => 17/461231 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461231
Structure and method for interlevel dielectric layer with regions of differing dielectric constant Aug 29, 2021 Issued
Array ( [id] => 18951014 [patent_doc_number] => 11894320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Semiconductor device package with stress reduction design and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/460668 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460668
Semiconductor device package with stress reduction design and method of forming the same Aug 29, 2021 Issued
Array ( [id] => 18230743 [patent_doc_number] => 20230069737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/458610 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458610
Semiconductor package and manufacturing method thereof Aug 26, 2021 Issued
Array ( [id] => 19029929 [patent_doc_number] => 11929293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor package with lid structure [patent_app_type] => utility [patent_app_number] => 17/406108 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 8878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406108
Semiconductor package with lid structure Aug 18, 2021 Issued
Array ( [id] => 17247139 [patent_doc_number] => 20210366884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/396308 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396308
Semiconductor package and method of fabricating the same Aug 5, 2021 Issued
Array ( [id] => 17389367 [patent_doc_number] => 20220037219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => HERMETIC SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/389294 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389294
Hermetic semiconductor packages Jul 28, 2021 Issued
Array ( [id] => 17389343 [patent_doc_number] => 20220037195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/386501 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386501
Method of forming semiconductor isolation structure and semiconductor isolation structure Jul 26, 2021 Issued
Array ( [id] => 19063312 [patent_doc_number] => 11942567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Light-emitting element, method of manufacturing the same and display device comprising light-emitting element [patent_app_type] => utility [patent_app_number] => 17/377266 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 12293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377266
Light-emitting element, method of manufacturing the same and display device comprising light-emitting element Jul 14, 2021 Issued
Array ( [id] => 18235981 [patent_doc_number] => 11600545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package [patent_app_type] => utility [patent_app_number] => 17/376570 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376570
Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package Jul 14, 2021 Issued
Array ( [id] => 17188873 [patent_doc_number] => 20210335758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => METHOD FOR PACKAGING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE STRUCTURE, AND PACKAGE [patent_app_type] => utility [patent_app_number] => 17/372537 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372537
METHOD FOR PACKAGING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE STRUCTURE, AND PACKAGE Jul 11, 2021 Abandoned
Array ( [id] => 17339439 [patent_doc_number] => 20220005770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => INTEGRATED STRUCTURES WITH ANTENNA ELEMENTS AND IC CHIPS EMPLOYING EDGE CONTACT CONNECTIONS [patent_app_type] => utility [patent_app_number] => 17/372797 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372797
Integrated structures with antenna elements and IC chips employing edge contact connections Jul 11, 2021 Issued
Array ( [id] => 17203553 [patent_doc_number] => 20210343648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => EMBEDDED COMPONENT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/373532 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373532
Embedded component package structure having a magnetically permeable layer Jul 11, 2021 Issued
Array ( [id] => 17900726 [patent_doc_number] => 20220310388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR BURIED LAYER [patent_app_type] => utility [patent_app_number] => 17/372930 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372930
Method of manufacturing at least one semiconductor device on or in a base semiconductor material disposed in a containment structure including a buried layer Jul 11, 2021 Issued
Array ( [id] => 17448243 [patent_doc_number] => 20220068748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/355799 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355799
Semiconductor device having semiconductor chip formed on wiring part, and method of manufacturing the same Jun 22, 2021 Issued
Array ( [id] => 18068192 [patent_doc_number] => 20220399280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => SOLDERABLE AND WIRE BONDABLE PART MARKING [patent_app_type] => utility [patent_app_number] => 17/345086 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345086
Solderable and wire bondable part marking Jun 10, 2021 Issued
Array ( [id] => 17115563 [patent_doc_number] => 20210296160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => Isolation Regions Including Two Layers and Method Forming Same [patent_app_type] => utility [patent_app_number] => 17/340734 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340734
Isolation regions including two layers and method forming same Jun 6, 2021 Issued
Array ( [id] => 19378262 [patent_doc_number] => 12069859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Semiconductor structure with high inter-layer dielectric layer and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/340888 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7307 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340888
Semiconductor structure with high inter-layer dielectric layer and manufacturing method thereof Jun 6, 2021 Issued
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