Search

Patrick Hamo

Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
1033
Issued Applications
757
Pending Applications
18
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7289742 [patent_doc_number] => 20040110341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Method for forming capacitor of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/608429 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2075 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110341.pdf [firstpage_image] =>[orig_patent_app_number] => 10608429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608429
Method for forming capacitor of semiconductor device Jun 29, 2003 Issued
Array ( [id] => 502962 [patent_doc_number] => 07205604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof' [patent_app_type] => utility [patent_app_number] => 10/463038 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205604.pdf [firstpage_image] =>[orig_patent_app_number] => 10463038 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463038
Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof Jun 16, 2003 Issued
Array ( [id] => 7130200 [patent_doc_number] => 20040041229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Power semiconductor device having high breakdown voltage, low on-resistance, and small switching loss and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/464059 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3404 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041229.pdf [firstpage_image] =>[orig_patent_app_number] => 10464059 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464059
Power semiconductor device having high breakdown voltage, low on-resistance, and small switching loss and method of forming the same Jun 16, 2003 Issued
Array ( [id] => 1107681 [patent_doc_number] => 06808994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Transistor structures and processes for forming same' [patent_app_type] => B1 [patent_app_number] => 10/463159 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808994.pdf [firstpage_image] =>[orig_patent_app_number] => 10463159 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463159
Transistor structures and processes for forming same Jun 16, 2003 Issued
Array ( [id] => 6723473 [patent_doc_number] => 20030205785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Low k film application for interlevel dielectric and method of cleaning etched features' [patent_app_type] => new [patent_app_number] => 10/462467 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3963 [patent_no_of_claims] => 112 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205785.pdf [firstpage_image] =>[orig_patent_app_number] => 10462467 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462467
Low k film application for interlevel dielectric and method of cleaning etched features Jun 15, 2003 Abandoned
Array ( [id] => 6966595 [patent_doc_number] => 20050233492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'METHOD OF FABRICATING SILICON-BASED MEMS DEVICES' [patent_app_type] => utility [patent_app_number] => 10/459619 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14676 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10459619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459619
Method of fabricating silicon-based MEMS devices Jun 11, 2003 Issued
Array ( [id] => 1169646 [patent_doc_number] => 06756652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Semiconductor memory device with efficiently laid-out internal interconnection lines' [patent_app_type] => B2 [patent_app_number] => 10/455420 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11915 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756652.pdf [firstpage_image] =>[orig_patent_app_number] => 10455420 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455420
Semiconductor memory device with efficiently laid-out internal interconnection lines Jun 5, 2003 Issued
Array ( [id] => 1112948 [patent_doc_number] => 06803298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of manufacturing a device with epitaxial base' [patent_app_type] => B2 [patent_app_number] => 10/455119 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3380 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803298.pdf [firstpage_image] =>[orig_patent_app_number] => 10455119 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455119
Method of manufacturing a device with epitaxial base Jun 3, 2003 Issued
Array ( [id] => 6725211 [patent_doc_number] => 20030207523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Chip design with power rails under transistors' [patent_app_type] => new [patent_app_number] => 10/453007 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2922 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207523.pdf [firstpage_image] =>[orig_patent_app_number] => 10453007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453007
Chip design with power rails under transistors Jun 2, 2003 Issued
Array ( [id] => 6723437 [patent_doc_number] => 20030205749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Localized masking for semiconductor structure development' [patent_app_type] => new [patent_app_number] => 10/453229 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7785 [patent_no_of_claims] => 168 [patent_no_of_ind_claims] => 34 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205749.pdf [firstpage_image] =>[orig_patent_app_number] => 10453229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453229
Localized masking for semiconductor structure development Jun 2, 2003 Issued
Array ( [id] => 6636056 [patent_doc_number] => 20030211680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication' [patent_app_type] => new [patent_app_number] => 10/452088 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6840 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211680.pdf [firstpage_image] =>[orig_patent_app_number] => 10452088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452088
Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication May 29, 2003 Issued
Array ( [id] => 935405 [patent_doc_number] => 06974754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Semiconductor device including ferroelectric capacitors and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 10/446829 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974754.pdf [firstpage_image] =>[orig_patent_app_number] => 10446829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446829
Semiconductor device including ferroelectric capacitors and fabricating method thereof May 28, 2003 Issued
Array ( [id] => 7310063 [patent_doc_number] => 20040031973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Process for manufacturing encapsulated optical sensors, and an encapsulated optical sensor manufactured using this process' [patent_app_type] => new [patent_app_number] => 10/446589 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3013 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20040031973.pdf [firstpage_image] =>[orig_patent_app_number] => 10446589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446589
Process for manufacturing encapsulated optical sensors, and an encapsulated optical sensor manufactured using this process May 26, 2003 Issued
Array ( [id] => 1138436 [patent_doc_number] => 06780766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Methods of forming regions of differing composition over a substrate' [patent_app_type] => B2 [patent_app_number] => 10/443354 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4704 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780766.pdf [firstpage_image] =>[orig_patent_app_number] => 10443354 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443354
Methods of forming regions of differing composition over a substrate May 20, 2003 Issued
Array ( [id] => 982230 [patent_doc_number] => 06927074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Asymmetric memory cell' [patent_app_type] => utility [patent_app_number] => 10/442627 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927074.pdf [firstpage_image] =>[orig_patent_app_number] => 10442627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442627
Asymmetric memory cell May 20, 2003 Issued
Array ( [id] => 456457 [patent_doc_number] => 07244651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Fabrication of an OTP-EPROM having reduced leakage current' [patent_app_type] => utility [patent_app_number] => 10/442524 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5666 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/244/07244651.pdf [firstpage_image] =>[orig_patent_app_number] => 10442524 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442524
Fabrication of an OTP-EPROM having reduced leakage current May 20, 2003 Issued
Array ( [id] => 1044071 [patent_doc_number] => 06867447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Ferroelectric memory cell and methods for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/441619 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 6673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867447.pdf [firstpage_image] =>[orig_patent_app_number] => 10441619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441619
Ferroelectric memory cell and methods for fabricating the same May 19, 2003 Issued
Array ( [id] => 6664229 [patent_doc_number] => 20030203555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Reduced area intersection between electrode and programming element' [patent_app_type] => new [patent_app_number] => 10/438146 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203555.pdf [firstpage_image] =>[orig_patent_app_number] => 10438146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438146
Reduced area intersection between electrode and programming element May 12, 2003 Issued
Array ( [id] => 732393 [patent_doc_number] => 07037736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Fluid ejection device' [patent_app_type] => utility [patent_app_number] => 10/436921 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 3773 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/037/07037736.pdf [firstpage_image] =>[orig_patent_app_number] => 10436921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436921
Fluid ejection device May 12, 2003 Issued
Array ( [id] => 1123509 [patent_doc_number] => 06794307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method for cleaning residual debris from semiconductor surfaces' [patent_app_type] => B2 [patent_app_number] => 10/427979 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4211 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794307.pdf [firstpage_image] =>[orig_patent_app_number] => 10427979 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427979
Method for cleaning residual debris from semiconductor surfaces May 1, 2003 Issued
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