
Patrick Hamo
Examiner (ID: 2096, Phone: (571)272-3492 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 1033 |
| Issued Applications | 757 |
| Pending Applications | 18 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7289742
[patent_doc_number] => 20040110341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Method for forming capacitor of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/608429
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20040110341.pdf
[firstpage_image] =>[orig_patent_app_number] => 10608429
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/608429 | Method for forming capacitor of semiconductor device | Jun 29, 2003 | Issued |
Array
(
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[patent_doc_number] => 07205604
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 10/463038
[patent_app_country] => US
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[pdf_file] => patents/07/205/07205604.pdf
[firstpage_image] =>[orig_patent_app_number] => 10463038
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/463038 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | Jun 16, 2003 | Issued |
Array
(
[id] => 7130200
[patent_doc_number] => 20040041229
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[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Power semiconductor device having high breakdown voltage, low on-resistance, and small switching loss and method of forming the same'
[patent_app_type] => new
[patent_app_number] => 10/464059
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10464059
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/464059 | Power semiconductor device having high breakdown voltage, low on-resistance, and small switching loss and method of forming the same | Jun 16, 2003 | Issued |
Array
(
[id] => 1107681
[patent_doc_number] => 06808994
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-26
[patent_title] => 'Transistor structures and processes for forming same'
[patent_app_type] => B1
[patent_app_number] => 10/463159
[patent_app_country] => US
[patent_app_date] => 2003-06-17
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Array
(
[id] => 6723473
[patent_doc_number] => 20030205785
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[patent_issue_date] => 2003-11-06
[patent_title] => 'Low k film application for interlevel dielectric and method of cleaning etched features'
[patent_app_type] => new
[patent_app_number] => 10/462467
[patent_app_country] => US
[patent_app_date] => 2003-06-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/462467 | Low k film application for interlevel dielectric and method of cleaning etched features | Jun 15, 2003 | Abandoned |
Array
(
[id] => 6966595
[patent_doc_number] => 20050233492
[patent_country] => US
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[patent_issue_date] => 2005-10-20
[patent_title] => 'METHOD OF FABRICATING SILICON-BASED MEMS DEVICES'
[patent_app_type] => utility
[patent_app_number] => 10/459619
[patent_app_country] => US
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Array
(
[id] => 1169646
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[patent_issue_date] => 2004-06-29
[patent_title] => 'Semiconductor memory device with efficiently laid-out internal interconnection lines'
[patent_app_type] => B2
[patent_app_number] => 10/455420
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/455420 | Semiconductor memory device with efficiently laid-out internal interconnection lines | Jun 5, 2003 | Issued |
Array
(
[id] => 1112948
[patent_doc_number] => 06803298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Method of manufacturing a device with epitaxial base'
[patent_app_type] => B2
[patent_app_number] => 10/455119
[patent_app_country] => US
[patent_app_date] => 2003-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[firstpage_image] =>[orig_patent_app_number] => 10455119
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/455119 | Method of manufacturing a device with epitaxial base | Jun 3, 2003 | Issued |
Array
(
[id] => 6725211
[patent_doc_number] => 20030207523
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[patent_issue_date] => 2003-11-06
[patent_title] => 'Chip design with power rails under transistors'
[patent_app_type] => new
[patent_app_number] => 10/453007
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10453007
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453007 | Chip design with power rails under transistors | Jun 2, 2003 | Issued |
Array
(
[id] => 6723437
[patent_doc_number] => 20030205749
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[patent_title] => 'Localized masking for semiconductor structure development'
[patent_app_type] => new
[patent_app_number] => 10/453229
[patent_app_country] => US
[patent_app_date] => 2003-06-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453229 | Localized masking for semiconductor structure development | Jun 2, 2003 | Issued |
Array
(
[id] => 6636056
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[patent_title] => 'Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication'
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Array
(
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Array
(
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Array
(
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Array
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Array
(
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Array
(
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Array
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Array
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[firstpage_image] =>[orig_patent_app_number] => 10427979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/427979 | Method for cleaning residual debris from semiconductor surfaces | May 1, 2003 | Issued |