Search

Patrick Moon

Examiner (ID: 19451)

Most Active Art Unit
2694
Art Unit(s)
2629, 2694
Total Applications
474
Issued Applications
283
Pending Applications
1
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17630658 [patent_doc_number] => 20220165673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/330416 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330416
Package structure and manufacturing method thereof May 25, 2021 Issued
Array ( [id] => 18008930 [patent_doc_number] => 20220367697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/322199 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322199
Group III-nitride transistors with back barrier structures and buried p-type layers and methods thereof May 16, 2021 Issued
Array ( [id] => 18008930 [patent_doc_number] => 20220367697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/322199 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322199
Group III-nitride transistors with back barrier structures and buried p-type layers and methods thereof May 16, 2021 Issued
Array ( [id] => 18008930 [patent_doc_number] => 20220367697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/322199 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322199
Group III-nitride transistors with back barrier structures and buried p-type layers and methods thereof May 16, 2021 Issued
Array ( [id] => 18008930 [patent_doc_number] => 20220367697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/322199 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322199
Group III-nitride transistors with back barrier structures and buried p-type layers and methods thereof May 16, 2021 Issued
Array ( [id] => 17070951 [patent_doc_number] => 20210273168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => VAPOR-DEPOSITION MASK, VAPOR-DEPOSITION METHOD AND METHOD FOR MANUFACTURING ORGANIC EL DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/321150 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321150
VAPOR-DEPOSITION MASK, VAPOR-DEPOSITION METHOD AND METHOD FOR MANUFACTURING ORGANIC EL DISPLAY APPARATUS May 13, 2021 Abandoned
Array ( [id] => 19314422 [patent_doc_number] => 12040247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Package system and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/320198 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320198
Package system and manufacturing method thereof May 12, 2021 Issued
Array ( [id] => 18951048 [patent_doc_number] => 11894354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Optoelectronic device package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/319948 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5080 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319948
Optoelectronic device package and method of manufacturing the same May 12, 2021 Issued
Array ( [id] => 17536741 [patent_doc_number] => 20220115350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/317309 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317309
Semiconductor package device May 10, 2021 Issued
Array ( [id] => 19108695 [patent_doc_number] => 11961809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Antenna apparatus and method [patent_app_type] => utility [patent_app_number] => 17/314368 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314368
Antenna apparatus and method May 6, 2021 Issued
Array ( [id] => 19081031 [patent_doc_number] => 11950425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Semiconductor memory device with mold structure [patent_app_type] => utility [patent_app_number] => 17/313649 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313649
Semiconductor memory device with mold structure May 5, 2021 Issued
Array ( [id] => 17040667 [patent_doc_number] => 20210257303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICALLY FORMED BUMPS AND METHODS OF ASSEMBLING SAME [patent_app_type] => utility [patent_app_number] => 17/306807 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306807
Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same May 2, 2021 Issued
Array ( [id] => 17318874 [patent_doc_number] => 20210407924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/306555 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306555
Semiconductor package May 2, 2021 Issued
Array ( [id] => 17986046 [patent_doc_number] => 20220352083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/244754 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244754
Method for forming chip package structure Apr 28, 2021 Issued
Array ( [id] => 19524058 [patent_doc_number] => 12125798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Semiconductor package and method [patent_app_type] => utility [patent_app_number] => 17/242704 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 11545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242704
Semiconductor package and method Apr 27, 2021 Issued
Array ( [id] => 18639549 [patent_doc_number] => 11764171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Integrated circuit structure and method [patent_app_type] => utility [patent_app_number] => 17/241715 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241715
Integrated circuit structure and method Apr 26, 2021 Issued
Array ( [id] => 17477489 [patent_doc_number] => 20220084993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/239956 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239956
Semiconductor package device Apr 25, 2021 Issued
Array ( [id] => 20360216 [patent_doc_number] => 12476222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Fan-out package structure [patent_app_type] => utility [patent_app_number] => 17/919280 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17919280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/919280
Fan-out package structure Apr 13, 2021 Issued
Array ( [id] => 17933290 [patent_doc_number] => 20220328416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/225832 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225832
Semiconductor package structure and method for manufacturing the same Apr 7, 2021 Issued
Array ( [id] => 19507895 [patent_doc_number] => 12119325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Semiconductor device assemblies with molded support substrates [patent_app_type] => utility [patent_app_number] => 17/224234 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4451 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224234
Semiconductor device assemblies with molded support substrates Apr 6, 2021 Issued
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