Search

Patrick O. Neill

Examiner (ID: 51, Phone: (571)270-1677 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2836, 2809, 2842
Total Applications
1143
Issued Applications
993
Pending Applications
56
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18048585 [patent_doc_number] => 11522545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Semiconductor device structure for wide supply voltage range [patent_app_type] => utility [patent_app_number] => 17/647475 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5704 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647475
Semiconductor device structure for wide supply voltage range Jan 9, 2022 Issued
Array ( [id] => 18123380 [patent_doc_number] => 20230008990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals [patent_app_type] => utility [patent_app_number] => 17/571690 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571690
Semiconductor device including a level shifter and method of mitigating a delay between input and output signals Jan 9, 2022 Issued
Array ( [id] => 20305888 [patent_doc_number] => 12451892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Phase-locked loop circuit and signal processing device [patent_app_type] => utility [patent_app_number] => 18/272271 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/272271
Phase-locked loop circuit and signal processing device Jan 6, 2022 Issued
Array ( [id] => 18548777 [patent_doc_number] => 11722140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods [patent_app_type] => utility [patent_app_number] => 17/646700 [patent_app_country] => US [patent_app_date] => 2021-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8847 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646700
Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods Dec 30, 2021 Issued
Array ( [id] => 18175656 [patent_doc_number] => 11575382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Phase lock loop circuit based signal generation in an optical measurement system [patent_app_type] => utility [patent_app_number] => 17/559774 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559774
Phase lock loop circuit based signal generation in an optical measurement system Dec 21, 2021 Issued
Array ( [id] => 17971962 [patent_doc_number] => 11489517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Dither generation for radio frequency sampling digital-to-analog converters [patent_app_type] => utility [patent_app_number] => 17/558794 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5012 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558794
Dither generation for radio frequency sampling digital-to-analog converters Dec 21, 2021 Issued
Array ( [id] => 17926493 [patent_doc_number] => 11469763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-11 [patent_title] => Low-pass filtering system having phase-locked loop [patent_app_type] => utility [patent_app_number] => 17/558131 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2142 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558131
Low-pass filtering system having phase-locked loop Dec 20, 2021 Issued
Array ( [id] => 18236548 [patent_doc_number] => 11601119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Radiation hardened flip-flop circuit for mitigating single event transients [patent_app_type] => utility [patent_app_number] => 17/552739 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552739
Radiation hardened flip-flop circuit for mitigating single event transients Dec 15, 2021 Issued
Array ( [id] => 19259410 [patent_doc_number] => 12019464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Digital system synchronization [patent_app_type] => utility [patent_app_number] => 17/552318 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552318
Digital system synchronization Dec 14, 2021 Issued
Array ( [id] => 19781302 [patent_doc_number] => 12230340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Shift register unit, gate driving circuit and display device [patent_app_type] => utility [patent_app_number] => 17/996293 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 11748 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 888 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17996293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/996293
Shift register unit, gate driving circuit and display device Nov 29, 2021 Issued
Array ( [id] => 18853668 [patent_doc_number] => 11851229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Systems and methods for counting and inspecting objects [patent_app_type] => utility [patent_app_number] => 17/527293 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6925 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527293
Systems and methods for counting and inspecting objects Nov 15, 2021 Issued
Array ( [id] => 18549448 [patent_doc_number] => 11722816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Signal processing circuit [patent_app_type] => utility [patent_app_number] => 17/526084 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4494 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526084
Signal processing circuit Nov 14, 2021 Issued
Array ( [id] => 19168971 [patent_doc_number] => 11984890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Scalable interconnected quantum architecture [patent_app_type] => utility [patent_app_number] => 17/525899 [patent_app_country] => US [patent_app_date] => 2021-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525899
Scalable interconnected quantum architecture Nov 12, 2021 Issued
Array ( [id] => 18913521 [patent_doc_number] => 11876516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Non-fighting level shifters [patent_app_type] => utility [patent_app_number] => 17/525345 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525345
Non-fighting level shifters Nov 11, 2021 Issued
Array ( [id] => 19063670 [patent_doc_number] => 11942933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Voltage level shifting with reduced timing degradation [patent_app_type] => utility [patent_app_number] => 17/521651 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9657 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521651
Voltage level shifting with reduced timing degradation Nov 7, 2021 Issued
Array ( [id] => 17969392 [patent_doc_number] => 11486916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Frequency synthesizer output cycle counter including ring encoder [patent_app_type] => utility [patent_app_number] => 17/515637 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515637
Frequency synthesizer output cycle counter including ring encoder Oct 31, 2021 Issued
Array ( [id] => 19285373 [patent_doc_number] => 20240221850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SHIFT REGISTER AND DRIVING METHOD THEREFOR, GATE DRIVER CIRCUIT, AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/913617 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17913617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/913617
Shift register and driving method therefor, gate driver circuit, and display apparatus Oct 27, 2021 Issued
Array ( [id] => 18001572 [patent_doc_number] => 11502690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Power supply generation for transmitter [patent_app_type] => utility [patent_app_number] => 17/512256 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512256
Power supply generation for transmitter Oct 26, 2021 Issued
Array ( [id] => 17390250 [patent_doc_number] => 20220038102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => TERMINATION CALIBRATION SCHEME USING A CURRENT MIRROR [patent_app_type] => utility [patent_app_number] => 17/502741 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502741
Termination calibration scheme using a current mirror Oct 14, 2021 Issued
Array ( [id] => 17861368 [patent_doc_number] => 11442524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Power management circuit and method [patent_app_type] => utility [patent_app_number] => 17/498321 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11954 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498321
Power management circuit and method Oct 10, 2021 Issued
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