Search

Patrick O. Neill

Examiner (ID: 10800, Phone: (571)270-1677 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2842, 2816, 2809
Total Applications
1117
Issued Applications
981
Pending Applications
44
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19486100 [patent_doc_number] => 20240334142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ELECTRONIC DEVICE WORN ON THE BODY, HEARING AID INSTRUMENT, AND VOLTAGE SUPPLY FOR SUCH A DEVICE [patent_app_type] => utility [patent_app_number] => 18/623196 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623196
ELECTRONIC DEVICE WORN ON THE BODY, HEARING AID INSTRUMENT, AND VOLTAGE SUPPLY FOR SUCH A DEVICE Mar 31, 2024 Pending
Array ( [id] => 20140053 [patent_doc_number] => 20250247097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => LEVEL SHIFTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/621244 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621244
Level shifter circuit Mar 28, 2024 Issued
Array ( [id] => 20249211 [patent_doc_number] => 20250298080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TEST MODE FOR GLITCH DETECTOIN AND BIT MISS IN A DIGITAL ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/609985 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609985
Test mode for glitch detection and bit miss in a digital isolator Mar 18, 2024 Issued
Array ( [id] => 19789073 [patent_doc_number] => 20250062752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => TEST APPARATUS AND TEST METHOD FOR DETECTING DEFECTS OF ELEMENTS INCLUDED IN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/602670 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602670
Test apparatus and test method for detecting defects of elements included in integrated circuit Mar 11, 2024 Issued
Array ( [id] => 19436784 [patent_doc_number] => 20240305282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/590903 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590903 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590903
Semiconductor device Feb 27, 2024 Issued
Array ( [id] => 20197419 [patent_doc_number] => 20250274129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MULTIPLYING DELAY LOCKED LOOP WITH HIGH TOLERANCE TO INPUT JITTER [patent_app_type] => utility [patent_app_number] => 18/584479 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584479
Multiplying delay locked loop with high tolerance to input jitter Feb 21, 2024 Issued
Array ( [id] => 20493909 [patent_doc_number] => 12535777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Frequency control assist device, frequency control device, and radio device [patent_app_type] => utility [patent_app_number] => 18/581756 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1191 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581756
Frequency control assist device, frequency control device, and radio device Feb 19, 2024 Issued
Array ( [id] => 19407982 [patent_doc_number] => 20240291493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => PHASE LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/581310 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581310
PHASE LOCKED LOOP CIRCUIT Feb 18, 2024 Abandoned
Array ( [id] => 19836409 [patent_doc_number] => 20250088195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => ELECTRONIC DEVICES INCLUDING LOCK DETECTING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/437546 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437546
Electronic devices including lock detecting circuit Feb 8, 2024 Issued
Array ( [id] => 19206947 [patent_doc_number] => 20240178846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/435323 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435323
PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT Feb 6, 2024 Pending
Array ( [id] => 19965404 [patent_doc_number] => 12334928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Level shifter [patent_app_type] => utility [patent_app_number] => 18/430700 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430700
Level shifter Feb 1, 2024 Issued
Array ( [id] => 20229622 [patent_doc_number] => 12418281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Low area and power multi-bit flip-flop [patent_app_type] => utility [patent_app_number] => 18/425722 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425722
Low area and power multi-bit flip-flop Jan 28, 2024 Issued
Array ( [id] => 19159466 [patent_doc_number] => 20240152173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => OUTPUT SIGNAL GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/416808 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416808
OUTPUT SIGNAL GENERATION CIRCUIT Jan 17, 2024 Abandoned
Array ( [id] => 19147071 [patent_doc_number] => 20240146117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => POWER TRANSMITTING APPARATUS, POWER RECEIVING APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/409671 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409671
POWER TRANSMITTING APPARATUS, POWER RECEIVING APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM Jan 9, 2024 Pending
Array ( [id] => 19771764 [patent_doc_number] => 20250053190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE CLOCK DISTRIBUTION NETWORK [patent_app_type] => utility [patent_app_number] => 18/406858 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406858
Clock distribution network, and semiconductor apparatus and semiconductor system using the clock distribution network Jan 7, 2024 Issued
Array ( [id] => 19270264 [patent_doc_number] => 20240213970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => APPARATUS FOR INPUTTING SIGNAL FROM COMMUNICATION LINE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/391720 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391720
Apparatus for inputting signal from communication line and method thereof Dec 20, 2023 Issued
Array ( [id] => 19532652 [patent_doc_number] => 20240356554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SYSTEMS AND METHODS FOR IMPROVED RELIABILITY IN VOLTAGE LEVEL SHIFTERS [patent_app_type] => utility [patent_app_number] => 18/542585 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/542585
Systems and methods for improved reliability in voltage level shifters Dec 14, 2023 Issued
Array ( [id] => 20111172 [patent_doc_number] => 12361906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Driver circuit, display device, and electronic device [patent_app_type] => utility [patent_app_number] => 18/522347 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 55 [patent_no_of_words] => 29603 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 708 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522347
Driver circuit, display device, and electronic device Nov 28, 2023 Issued
Array ( [id] => 19053542 [patent_doc_number] => 20240095511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => OUTPUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/522153 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522153
Output circuit Nov 27, 2023 Issued
Array ( [id] => 20176401 [patent_doc_number] => 12395161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Flip-flop based on clock signal and pulse signal [patent_app_type] => utility [patent_app_number] => 18/507867 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507867
Flip-flop based on clock signal and pulse signal Nov 12, 2023 Issued
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