Patrick O. Neill

Array ( [id] => 18790172 [patent_doc_number] => 20230378957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => LEVEL CONVERTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/364950 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19758720 [patent_doc_number] => 20250047285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => THIN OXIDE LOW VOLTAGE TO HIGH VOLTAGE LEVEL SHIFTERS [patent_app_type] => utility [patent_app_number] => 18/229152 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19385520 [patent_doc_number] => 20240275390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => FREQUENCY DETECTOR AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/361059 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19906394 [patent_doc_number] => 12283409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Variable circuit [patent_app_type] => utility [patent_app_number] => 18/361313 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 5936 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18944383 [patent_doc_number] => 20240039522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DIFFERENTIAL INTERFACE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/357562 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19647938 [patent_doc_number] => 20240422458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => METHODS AND CIRCUITS FOR CONTROLLING MULTICYCLE PATH IN SERIALIZER INTERFACE [patent_app_type] => utility [patent_app_number] => 18/355731 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20389673 [patent_doc_number] => 12489411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Hot switching spur suppression [patent_app_type] => utility [patent_app_number] => 18/223976 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19727670 [patent_doc_number] => 20250030421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => CHANNEL BASED CONFIGURABLE CML, LVDS, OPEN DRAIN OUTPUT [patent_app_type] => utility [patent_app_number] => 18/223371 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19885507 [patent_doc_number] => 12271220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Managing multi-phase clock signals for integrated circuit devices [patent_app_type] => utility [patent_app_number] => 18/345725 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19538103 [patent_doc_number] => 12130656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Skew-correcting clock buffer [patent_app_type] => utility [patent_app_number] => 18/343841 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19900678 [patent_doc_number] => 12278623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Power on reset (POR) circuit [patent_app_type] => utility [patent_app_number] => 18/332522 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18959805 [patent_doc_number] => 20240048132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => DUAL-EDGE-TRIGGERED FLIP-FLOP [patent_app_type] => utility [patent_app_number] => 18/330731 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19720982 [patent_doc_number] => 12206532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-21 [patent_title] => Wireline receiver sampling circuit [patent_app_type] => utility [patent_app_number] => 18/329774 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19400207 [patent_doc_number] => 12074603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-27 [patent_title] => Leakage-free dummy cell for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/313384 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19101699 [patent_doc_number] => 20240120927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PHASE-LOCKED LOOP DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/142939 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19547312 [patent_doc_number] => 20240364348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SYNCHRONIZATION OF MULTIPLE CLOCK DIVIDERS BY USING LOWER-FREQUENCY CLOCKS AND SLIPPING CYCLES [patent_app_type] => utility [patent_app_number] => 18/308783 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19329384 [patent_doc_number] => 12047079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Flip-flop circuit and method [patent_app_type] => utility [patent_app_number] => 18/302178 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20118712 [patent_doc_number] => 12368434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => D flip-flop having multiplexer function [patent_app_type] => utility [patent_app_number] => 18/272053 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 3642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 531 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19944191 [patent_doc_number] => 12316334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection [patent_app_type] => utility [patent_app_number] => 18/194049 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18697212 [patent_doc_number] => 20230327671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => VOLTAGE LEVEL SHIFTER AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/185399 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185399 [rel_patent_id] =>[rel_patent_doc_number] =>)