
Patrick O. Neill
Examiner (ID: 17493, Phone: (571)270-1677 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2842, 2809, 2816 |
| Total Applications | 1122 |
| Issued Applications | 986 |
| Pending Applications | 43 |
| Abandoned Applications | 115 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19547312
[patent_doc_number] => 20240364348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => SYNCHRONIZATION OF MULTIPLE CLOCK DIVIDERS BY USING LOWER-FREQUENCY CLOCKS AND SLIPPING CYCLES
[patent_app_type] => utility
[patent_app_number] => 18/308783
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10843
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308783
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/308783 | Synchronization of multiple clock dividers by using lower-frequency clocks and slipping cycles | Apr 27, 2023 | Issued |
Array
(
[id] => 19329384
[patent_doc_number] => 12047079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-23
[patent_title] => Flip-flop circuit and method
[patent_app_type] => utility
[patent_app_number] => 18/302178
[patent_app_country] => US
[patent_app_date] => 2023-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 12477
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302178
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/302178 | Flip-flop circuit and method | Apr 17, 2023 | Issued |
Array
(
[id] => 20118712
[patent_doc_number] => 12368434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => D flip-flop having multiplexer function
[patent_app_type] => utility
[patent_app_number] => 18/272053
[patent_app_country] => US
[patent_app_date] => 2023-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 33
[patent_no_of_words] => 3642
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 531
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272053
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/272053 | D flip-flop having multiplexer function | Apr 11, 2023 | Issued |
Array
(
[id] => 19944191
[patent_doc_number] => 12316334
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection
[patent_app_type] => utility
[patent_app_number] => 18/194049
[patent_app_country] => US
[patent_app_date] => 2023-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 5146
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194049
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/194049 | Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection | Mar 30, 2023 | Issued |
Array
(
[id] => 18697212
[patent_doc_number] => 20230327671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => VOLTAGE LEVEL SHIFTER AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/185399
[patent_app_country] => US
[patent_app_date] => 2023-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5849
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185399
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/185399 | Voltage level shifter and operation method thereof | Mar 16, 2023 | Issued |
Array
(
[id] => 19782085
[patent_doc_number] => 12231132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Systems and methods for PLL duty cycle calibration
[patent_app_type] => utility
[patent_app_number] => 18/120838
[patent_app_country] => US
[patent_app_date] => 2023-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 11566
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120838
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/120838 | Systems and methods for PLL duty cycle calibration | Mar 12, 2023 | Issued |
Array
(
[id] => 18488051
[patent_doc_number] => 20230215397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => Driver Circuit, Display Device, And Electronic Device
[patent_app_type] => utility
[patent_app_number] => 18/120489
[patent_app_country] => US
[patent_app_date] => 2023-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120489
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/120489 | Driver circuit, display device, and electronic device | Mar 12, 2023 | Issued |
Array
(
[id] => 19055333
[patent_doc_number] => 20240097302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => DIGITAL ISOLATOR
[patent_app_type] => utility
[patent_app_number] => 18/118271
[patent_app_country] => US
[patent_app_date] => 2023-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9311
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118271
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/118271 | Digital isolator | Mar 6, 2023 | Issued |
Array
(
[id] => 19734319
[patent_doc_number] => 12212327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
[patent_app_type] => utility
[patent_app_number] => 18/114847
[patent_app_country] => US
[patent_app_date] => 2023-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7908
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114847
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/114847 | Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods | Feb 26, 2023 | Issued |
Array
(
[id] => 19393565
[patent_doc_number] => 20240283435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => Scan Flip Flop
[patent_app_type] => utility
[patent_app_number] => 18/171074
[patent_app_country] => US
[patent_app_date] => 2023-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171074
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/171074 | Scan Flip Flop | Feb 16, 2023 | Abandoned |
Array
(
[id] => 19391175
[patent_doc_number] => 20240281045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => Voltage Droop Monitor
[patent_app_type] => utility
[patent_app_number] => 18/170864
[patent_app_country] => US
[patent_app_date] => 2023-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170864
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/170864 | Voltage Droop Monitor | Feb 16, 2023 | Abandoned |
Array
(
[id] => 19679979
[patent_doc_number] => 12191856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Input buffer circuit and semiconductor system including the same
[patent_app_type] => utility
[patent_app_number] => 18/107934
[patent_app_country] => US
[patent_app_date] => 2023-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4522
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107934
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/107934 | Input buffer circuit and semiconductor system including the same | Feb 8, 2023 | Issued |
Array
(
[id] => 18424721
[patent_doc_number] => 20230179186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-08
[patent_title] => SENSE AMPLIFIER FOR COUPLING EFFECT REDUCTION
[patent_app_type] => utility
[patent_app_number] => 18/163461
[patent_app_country] => US
[patent_app_date] => 2023-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13180
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163461
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/163461 | Sense amplifier for coupling effect reduction | Feb 1, 2023 | Issued |
Array
(
[id] => 19365018
[patent_doc_number] => 20240267052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 18/104916
[patent_app_country] => US
[patent_app_date] => 2023-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9143
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104916
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/104916 | PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR (DCO) GAIN CALIBRATION CIRCUITS AND RELATED METHODS | Feb 1, 2023 | Pending |
Array
(
[id] => 19618001
[patent_doc_number] => 20240403681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => Suppressing Superconducting Qubit Measurement-Induced State Transitions
[patent_app_type] => utility
[patent_app_number] => 18/161365
[patent_app_country] => US
[patent_app_date] => 2023-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15223
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161365
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/161365 | Suppressing superconducting qubit measurement-induced state transitions | Jan 29, 2023 | Issued |
Array
(
[id] => 19214163
[patent_doc_number] => 12003242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-04
[patent_title] => Integrated circuit having latch with transistors of different gate widths
[patent_app_type] => utility
[patent_app_number] => 18/160630
[patent_app_country] => US
[patent_app_date] => 2023-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 12234
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160630
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/160630 | Integrated circuit having latch with transistors of different gate widths | Jan 26, 2023 | Issued |
Array
(
[id] => 20116905
[patent_doc_number] => 12366605
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Area, cost, and time-effective scan coverage improvement
[patent_app_type] => utility
[patent_app_number] => 18/100975
[patent_app_country] => US
[patent_app_date] => 2023-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3535
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100975
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/100975 | Area, cost, and time-effective scan coverage improvement | Jan 23, 2023 | Issued |
Array
(
[id] => 18981831
[patent_doc_number] => 11907003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Output signal generation circuit
[patent_app_type] => utility
[patent_app_number] => 18/156148
[patent_app_country] => US
[patent_app_date] => 2023-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5619
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156148
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/156148 | Output signal generation circuit | Jan 17, 2023 | Issued |
Array
(
[id] => 18735533
[patent_doc_number] => 11804274
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Shift register circuit, active matrix substrate, and display apparatus
[patent_app_type] => utility
[patent_app_number] => 18/097173
[patent_app_country] => US
[patent_app_date] => 2023-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 10571
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 500
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097173
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/097173 | Shift register circuit, active matrix substrate, and display apparatus | Jan 12, 2023 | Issued |
Array
(
[id] => 20227881
[patent_doc_number] => 12416529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Temperature sensor circuits and control circuits and method for temperature sensor circuits
[patent_app_type] => utility
[patent_app_number] => 18/150772
[patent_app_country] => US
[patent_app_date] => 2023-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6576
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150772
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/150772 | Temperature sensor circuits and control circuits and method for temperature sensor circuits | Jan 4, 2023 | Issued |