Patrick R. Holecek

Array ( [id] => 3041604 [patent_doc_number] => 05349669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Data write control means' [patent_app_type] => 1 [patent_app_number] => 8/012618 [patent_app_country] => US [patent_app_date] => 1993-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4853 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349669.pdf [firstpage_image] =>[orig_patent_app_number] => 012618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3016617 [patent_doc_number] => 05375223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Single register arbiter circuit' [patent_app_type] => 1 [patent_app_number] => 8/001372 [patent_app_country] => US [patent_app_date] => 1993-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4615 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375223.pdf [firstpage_image] =>[orig_patent_app_number] => 001372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3494899 [patent_doc_number] => 05446847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Programmable system bus priority network' [patent_app_type] => 1 [patent_app_number] => 8/000531 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4471 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446847.pdf [firstpage_image] =>[orig_patent_app_number] => 000531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3564828 [patent_doc_number] => 05493683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Register for identifying processor characteristics' [patent_app_type] => 1 [patent_app_number] => 7/997879 [patent_app_country] => US [patent_app_date] => 1992-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4359 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493683.pdf [firstpage_image] =>[orig_patent_app_number] => 997879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3533004 [patent_doc_number] => 05490277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Digital computation integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/994430 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4409 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490277.pdf [firstpage_image] =>[orig_patent_app_number] => 994430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3471805 [patent_doc_number] => 05442754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Receiving control logic system for dual bus network' [patent_app_type] => 1 [patent_app_number] => 7/985662 [patent_app_country] => US [patent_app_date] => 1992-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 18400 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442754.pdf [firstpage_image] =>[orig_patent_app_number] => 985662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3501334 [patent_doc_number] => 05471588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource' [patent_app_type] => 1 [patent_app_number] => 7/981889 [patent_app_country] => US [patent_app_date] => 1992-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2414 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471588.pdf [firstpage_image] =>[orig_patent_app_number] => 981889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3465077 [patent_doc_number] => 05379385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Method and means for effectuating rule based I/O data transfer address control via address control words' [patent_app_type] => 1 [patent_app_number] => 7/978051 [patent_app_country] => US [patent_app_date] => 1992-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5103 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379385.pdf [firstpage_image] =>[orig_patent_app_number] => 978051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3042524 [patent_doc_number] => 05317752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Fault-tolerant computer system with auto-restart after power-fall' [patent_app_type] => 1 [patent_app_number] => 7/977734 [patent_app_country] => US [patent_app_date] => 1992-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 20855 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317752.pdf [firstpage_image] =>[orig_patent_app_number] => 977734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3108335 [patent_doc_number] => 05291608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Display adapter event handler with rendering context manager' [patent_app_type] => 1 [patent_app_number] => 7/973940 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 39 [patent_no_of_words] => 12967 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291608.pdf [firstpage_image] =>[orig_patent_app_number] => 973940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3503228 [patent_doc_number] => 05440746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'System and method for synchronizing processors in a parallel processing environment' [patent_app_type] => 1 [patent_app_number] => 7/972699 [patent_app_country] => US [patent_app_date] => 1992-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5019 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440746.pdf [firstpage_image] =>[orig_patent_app_number] => 972699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544565 [patent_doc_number] => 05584028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Method and device for processing multiple, asynchronous interrupt signals' [patent_app_type] => 1 [patent_app_number] => 7/966620 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3277 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584028.pdf [firstpage_image] =>[orig_patent_app_number] => 966620 [rel_patent_id] =>[rel_patent_doc_number] =>)