Patrick R. Holecek

Array ( [id] => 3053122 [patent_doc_number] => 05377332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Bus arbitration algorithm and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/921456 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377332.pdf [firstpage_image] =>[orig_patent_app_number] => 921456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3070289 [patent_doc_number] => 05339402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'System for connecting an IC memory card to a central processing unit of a computer' [patent_app_type] => 1 [patent_app_number] => 7/920912 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339402.pdf [firstpage_image] =>[orig_patent_app_number] => 920912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3428325 [patent_doc_number] => 05394552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Docking system for enhancing computer functionality' [patent_app_type] => 1 [patent_app_number] => 7/910275 [patent_app_country] => US [patent_app_date] => 1992-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 4215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394552.pdf [firstpage_image] =>[orig_patent_app_number] => 910275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3024334 [patent_doc_number] => 05276847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Method for locking and unlocking a computer address' [patent_app_type] => 1 [patent_app_number] => 7/912033 [patent_app_country] => US [patent_app_date] => 1992-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5724 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276847.pdf [firstpage_image] =>[orig_patent_app_number] => 912033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2951109 [patent_doc_number] => 05261057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'I/O bus to system interface' [patent_app_type] => 1 [patent_app_number] => 7/912052 [patent_app_country] => US [patent_app_date] => 1992-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 10772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261057.pdf [firstpage_image] =>[orig_patent_app_number] => 912052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3020966 [patent_doc_number] => 05355452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Dual bus local area network interfacing system' [patent_app_type] => 1 [patent_app_number] => 7/907955 [patent_app_country] => US [patent_app_date] => 1992-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355452.pdf [firstpage_image] =>[orig_patent_app_number] => 907955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2951487 [patent_doc_number] => 05261075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Optical recording medium access system' [patent_app_type] => 1 [patent_app_number] => 7/908573 [patent_app_country] => US [patent_app_date] => 1992-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1652 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261075.pdf [firstpage_image] =>[orig_patent_app_number] => 908573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3569042 [patent_doc_number] => 05502821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method of determining devices requesting the transfer of data signals on a bus' [patent_app_type] => 1 [patent_app_number] => 7/909511 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5068 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502821.pdf [firstpage_image] =>[orig_patent_app_number] => 909511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3094826 [patent_doc_number] => 05280590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Logic support chip for AT-type computer with improved bus architecture' [patent_app_type] => 1 [patent_app_number] => 7/902317 [patent_app_country] => US [patent_app_date] => 1992-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3749 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280590.pdf [firstpage_image] =>[orig_patent_app_number] => 902317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3501896 [patent_doc_number] => 05471624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Apparatus and method for suspending and resuming software applications on a computer' [patent_app_type] => 1 [patent_app_number] => 7/895131 [patent_app_country] => US [patent_app_date] => 1992-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 9364 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471624.pdf [firstpage_image] =>[orig_patent_app_number] => 895131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3992419 [patent_doc_number] => 05918007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Trusted personal computer system with limited accessibility' [patent_app_type] => 1 [patent_app_number] => 7/889325 [patent_app_country] => US [patent_app_date] => 1992-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7850 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918007.pdf [firstpage_image] =>[orig_patent_app_number] => 889325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2963332 [patent_doc_number] => 05263139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems' [patent_app_type] => 1 [patent_app_number] => 7/886045 [patent_app_country] => US [patent_app_date] => 1992-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2890 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263139.pdf [firstpage_image] =>[orig_patent_app_number] => 886045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3456512 [patent_doc_number] => 05388224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Processor identification mechanism for a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/873924 [patent_app_country] => US [patent_app_date] => 1992-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 39506 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388224.pdf [firstpage_image] =>[orig_patent_app_number] => 873924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3077911 [patent_doc_number] => 05295247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Local IDE (integrated drive electronics) bus architecture' [patent_app_type] => 1 [patent_app_number] => 7/870623 [patent_app_country] => US [patent_app_date] => 1992-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1961 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295247.pdf [firstpage_image] =>[orig_patent_app_number] => 870623 [rel_patent_id] =>[rel_patent_doc_number] =>)