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Paul A. Budd

Examiner (ID: 3830)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
569
Issued Applications
466
Pending Applications
2
Abandoned Applications
101

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9202345 [patent_doc_number] => 20140001523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'STRESS ENGINEERING TO REDUCE DARK CURRENT OF CMOS IMAGE SENSORS' [patent_app_type] => utility [patent_app_number] => 14/018178 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018178
Methods of stress engineering to reduce dark current of CMOS image sensors Sep 3, 2013 Issued
Array ( [id] => 9639399 [patent_doc_number] => 20140217509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Diode Structure and Method for Gate All Around Silicon Nanowire Technologies' [patent_app_type] => utility [patent_app_number] => 13/969820 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4598 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969820
Diode structure for gate all around silicon nanowire technologies Aug 18, 2013 Issued
Array ( [id] => 10624360 [patent_doc_number] => 09343310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Methods of forming conductors and semiconductors on a substrate' [patent_app_type] => utility [patent_app_number] => 13/928341 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6224 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928341 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/928341
Methods of forming conductors and semiconductors on a substrate Jun 25, 2013 Issued
Array ( [id] => 9259789 [patent_doc_number] => 20130341718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'POWER SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/928186 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/928186
Level shift power semiconductor device Jun 25, 2013 Issued
Array ( [id] => 10577049 [patent_doc_number] => 09299698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Semiconductor structure with multiple transistors having various threshold voltages' [patent_app_type] => utility [patent_app_number] => 13/926555 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 33 [patent_no_of_words] => 10229 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926555
Semiconductor structure with multiple transistors having various threshold voltages Jun 24, 2013 Issued
Array ( [id] => 9394021 [patent_doc_number] => 20140091427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'ELECTRICAL FUSE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/926710 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6148 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926710 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926710
Electrical fuse and method of fabricating the same Jun 24, 2013 Issued
Array ( [id] => 9209568 [patent_doc_number] => 20140008745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/926355 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10245 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926355
SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS Jun 24, 2013 Abandoned
Array ( [id] => 9135026 [patent_doc_number] => 20130295741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/913012 [patent_app_country] => US [patent_app_date] => 2013-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7048 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/913012
Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion Jun 6, 2013 Issued
Array ( [id] => 9844145 [patent_doc_number] => 08946060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Methods of manufacturing strained semiconductor devices with facets' [patent_app_type] => utility [patent_app_number] => 13/889846 [patent_app_country] => US [patent_app_date] => 2013-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13889846 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/889846
Methods of manufacturing strained semiconductor devices with facets May 7, 2013 Issued
Array ( [id] => 9038349 [patent_doc_number] => 20130240987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SEMICONDUCTOR FIELD EFFECT POWER SWITCHING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/870617 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 88 [patent_no_of_words] => 25875 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870617 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/870617
Semiconductor field effect power switching device Apr 24, 2013 Issued
Array ( [id] => 9034391 [patent_doc_number] => 20130237029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/868440 [patent_app_country] => US [patent_app_date] => 2013-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13258 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13868440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/868440
Method for manufacturing a non-volatile semiconductor memory device Apr 22, 2013 Issued
Array ( [id] => 10172073 [patent_doc_number] => 09202784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Semiconductor integrated circuit capacitance device' [patent_app_type] => utility [patent_app_number] => 13/865899 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 64 [patent_no_of_words] => 17571 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865899
Semiconductor integrated circuit capacitance device Apr 17, 2013 Issued
Array ( [id] => 10172197 [patent_doc_number] => 09202909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Power MOSFET semiconductor' [patent_app_type] => utility [patent_app_number] => 13/852127 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 78 [patent_no_of_words] => 18787 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852127
Power MOSFET semiconductor Mar 27, 2013 Issued
Array ( [id] => 10584032 [patent_doc_number] => 09306161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'Fabrication methods of conducting bridge random access memory (CBRAM) device structures' [patent_app_type] => utility [patent_app_number] => 13/845922 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 91 [patent_no_of_words] => 11240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845922
Fabrication methods of conducting bridge random access memory (CBRAM) device structures Mar 17, 2013 Issued
Array ( [id] => 8986280 [patent_doc_number] => 20130213561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'DEVICE AND DEVICE MANUFACTURE METHOD' [patent_app_type] => utility [patent_app_number] => 13/797521 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7349 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13797521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/797521
Manufcaturing method for room-temperature substrate bonding Mar 11, 2013 Issued
Array ( [id] => 8904288 [patent_doc_number] => 20130171791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD' [patent_app_type] => utility [patent_app_number] => 13/779163 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13779163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/779163
Manufacture method of a high voltage MOS semiconductor device Feb 26, 2013 Issued
Array ( [id] => 9817612 [patent_doc_number] => 08927397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Diode structure and method for gate all around silicon nanowire technologies' [patent_app_type] => utility [patent_app_number] => 13/761453 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761453
Diode structure and method for gate all around silicon nanowire technologies Feb 6, 2013 Issued
Array ( [id] => 8973763 [patent_doc_number] => 20130207193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/761931 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 20115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761931 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761931
Semiconductor transistor device with barrier interconnects Feb 6, 2013 Issued
Array ( [id] => 9334995 [patent_doc_number] => 20140061777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/760755 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760755
Semiconductor tunnel FET transistor device Feb 5, 2013 Issued
Array ( [id] => 10189640 [patent_doc_number] => 09219070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => '3-D memory arrays' [patent_app_type] => utility [patent_app_number] => 13/759627 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3274 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759627
3-D memory arrays Feb 4, 2013 Issued
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