
Paul A. Budd
Examiner (ID: 11378)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 569 |
| Issued Applications | 466 |
| Pending Applications | 2 |
| Abandoned Applications | 101 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6929461
[patent_doc_number] => 20050280495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Fuse-data reading circuit'
[patent_app_type] => utility
[patent_app_number] => 11/138712
[patent_app_country] => US
[patent_app_date] => 2005-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4522
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0280/20050280495.pdf
[firstpage_image] =>[orig_patent_app_number] => 11138712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/138712 | Fuse-data reading circuit | May 24, 2005 | Issued |
Array
(
[id] => 7205861
[patent_doc_number] => 20050258427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Vertical thin film transistor electronics'
[patent_app_type] => utility
[patent_app_number] => 11/133411
[patent_app_country] => US
[patent_app_date] => 2005-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9055
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20050258427.pdf
[firstpage_image] =>[orig_patent_app_number] => 11133411
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/133411 | Vertical thin film transistor electronics | May 19, 2005 | Abandoned |
Array
(
[id] => 6955641
[patent_doc_number] => 20050212011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Architecture for mask programmable devices'
[patent_app_type] => utility
[patent_app_number] => 11/132962
[patent_app_country] => US
[patent_app_date] => 2005-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4753
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20050212011.pdf
[firstpage_image] =>[orig_patent_app_number] => 11132962
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/132962 | Architecture for mask programmable devices | May 18, 2005 | Abandoned |
Array
(
[id] => 337987
[patent_doc_number] => 07504328
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-17
[patent_title] => 'Schottky barrier source/drain n-mosfet using ytterbium silicide'
[patent_app_type] => utility
[patent_app_number] => 11/126031
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2424
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/504/07504328.pdf
[firstpage_image] =>[orig_patent_app_number] => 11126031
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/126031 | Schottky barrier source/drain n-mosfet using ytterbium silicide | May 9, 2005 | Issued |
Array
(
[id] => 5724226
[patent_doc_number] => 20060054986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Image sensor with multilevel binary optics element'
[patent_app_type] => utility
[patent_app_number] => 11/117232
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 857
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20060054986.pdf
[firstpage_image] =>[orig_patent_app_number] => 11117232
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/117232 | Image sensor with multilevel binary optics element | Apr 27, 2005 | Abandoned |
Array
(
[id] => 6942610
[patent_doc_number] => 20050194658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-08
[patent_title] => 'Strained silicon structure'
[patent_app_type] => utility
[patent_app_number] => 11/114981
[patent_app_country] => US
[patent_app_date] => 2005-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3890
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20050194658.pdf
[firstpage_image] =>[orig_patent_app_number] => 11114981
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/114981 | Strained silicon structure | Apr 25, 2005 | Issued |
Array
(
[id] => 869618
[patent_doc_number] => 07365396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-29
[patent_title] => 'SOI SRAM products with reduced floating body effect'
[patent_app_type] => utility
[patent_app_number] => 11/105452
[patent_app_country] => US
[patent_app_date] => 2005-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3604
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/365/07365396.pdf
[firstpage_image] =>[orig_patent_app_number] => 11105452
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/105452 | SOI SRAM products with reduced floating body effect | Apr 13, 2005 | Issued |
Array
(
[id] => 5851293
[patent_doc_number] => 20060234484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'METHOD AND STRUCTURE FOR ION IMPLANTATION BY ION SCATTERING'
[patent_app_type] => utility
[patent_app_number] => 10/907752
[patent_app_country] => US
[patent_app_date] => 2005-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3993
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20060234484.pdf
[firstpage_image] =>[orig_patent_app_number] => 10907752
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907752 | METHOD AND STRUCTURE FOR ION IMPLANTATION BY ION SCATTERING | Apr 13, 2005 | Abandoned |
Array
(
[id] => 803273
[patent_doc_number] => 07422977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Copper adhesion improvement device and method'
[patent_app_type] => utility
[patent_app_number] => 11/095567
[patent_app_country] => US
[patent_app_date] => 2005-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 4795
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/422/07422977.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095567
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095567 | Copper adhesion improvement device and method | Mar 31, 2005 | Issued |
Array
(
[id] => 7132822
[patent_doc_number] => 20050179053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Solid-state image device and production method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/094072
[patent_app_country] => US
[patent_app_date] => 2005-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6139
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20050179053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11094072
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/094072 | Solid-state image device | Mar 29, 2005 | Issued |
Array
(
[id] => 122772
[patent_doc_number] => 07709899
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Semiconductor apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/594542
[patent_app_country] => US
[patent_app_date] => 2005-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 3408
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/709/07709899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10594542
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/594542 | Semiconductor apparatus | Mar 28, 2005 | Issued |
Array
(
[id] => 380315
[patent_doc_number] => 07309891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-18
[patent_title] => 'Non-volatile and memory semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/087592
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 45
[patent_no_of_words] => 14936
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/309/07309891.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087592
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087592 | Non-volatile and memory semiconductor integrated circuit | Mar 23, 2005 | Issued |
Array
(
[id] => 5697530
[patent_doc_number] => 20060214214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Scalable spilt-gate flash memory cell with high source-coupling ratio'
[patent_app_type] => utility
[patent_app_number] => 11/088492
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3241
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20060214214.pdf
[firstpage_image] =>[orig_patent_app_number] => 11088492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/088492 | Scalable split-gate flash memory cell with high source-coupling ratio | Mar 23, 2005 | Issued |
Array
(
[id] => 539284
[patent_doc_number] => 07176490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/087652
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 107
[patent_no_of_words] => 24978
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/176/07176490.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087652
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087652 | Semiconductor device | Mar 23, 2005 | Issued |
Array
(
[id] => 7108439
[patent_doc_number] => 20050205892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/081622
[patent_app_country] => US
[patent_app_date] => 2005-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7449
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20050205892.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081622
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081622 | HEMT transistor semiconductor device | Mar 16, 2005 | Issued |
Array
(
[id] => 5877994
[patent_doc_number] => 20060027832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Bidirectional photothyristor chip, optical lighting coupler, and solid state relay'
[patent_app_type] => utility
[patent_app_number] => 11/080522
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 25136
[patent_no_of_claims] => 78
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20060027832.pdf
[firstpage_image] =>[orig_patent_app_number] => 11080522
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/080522 | Bidirectional photothyristor chip, optical lighting coupler, and solid state relay | Mar 15, 2005 | Issued |
Array
(
[id] => 6955711
[patent_doc_number] => 20050212081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Fuse region of a semiconductor device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/079302
[patent_app_country] => US
[patent_app_date] => 2005-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4241
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20050212081.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079302
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079302 | Fuse region of a semiconductor region | Mar 14, 2005 | Issued |
Array
(
[id] => 289332
[patent_doc_number] => 07547948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-16
[patent_title] => 'Semiconductor device including bipolar junction transistor with protected emitter-base junction'
[patent_app_type] => utility
[patent_app_number] => 11/073762
[patent_app_country] => US
[patent_app_date] => 2005-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 33
[patent_no_of_words] => 8323
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/547/07547948.pdf
[firstpage_image] =>[orig_patent_app_number] => 11073762
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/073762 | Semiconductor device including bipolar junction transistor with protected emitter-base junction | Mar 7, 2005 | Issued |
Array
(
[id] => 495833
[patent_doc_number] => 07211865
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Silicided body contact SOI device'
[patent_app_type] => utility
[patent_app_number] => 11/074362
[patent_app_country] => US
[patent_app_date] => 2005-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 4555
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/211/07211865.pdf
[firstpage_image] =>[orig_patent_app_number] => 11074362
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/074362 | Silicided body contact SOI device | Mar 6, 2005 | Issued |
Array
(
[id] => 5680961
[patent_doc_number] => 20060197228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'SINGLE MASK PROCESS FOR VARIABLE THICKNESS DUAL DAMASCENE STRUCTURES, OTHER GREY-MASKING PROCESSES, AND STRUCTURES MADE USING GREY-MASKING'
[patent_app_type] => utility
[patent_app_number] => 10/906752
[patent_app_country] => US
[patent_app_date] => 2005-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 4675
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20060197228.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906752
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906752 | SINGLE MASK PROCESS FOR VARIABLE THICKNESS DUAL DAMASCENE STRUCTURES, OTHER GREY-MASKING PROCESSES, AND STRUCTURES MADE USING GREY-MASKING | Mar 3, 2005 | Abandoned |