Search

Paul A. Budd

Examiner (ID: 16043)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
569
Issued Applications
466
Pending Applications
2
Abandoned Applications
101

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 217507 [patent_doc_number] => 07612419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Wafer, semiconductor chip, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/071281 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5624 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612419.pdf [firstpage_image] =>[orig_patent_app_number] => 11071281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071281
Wafer, semiconductor chip, and semiconductor device Mar 3, 2005 Issued
Array ( [id] => 6942600 [patent_doc_number] => 20050194648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Semiconductor device including a transistor having low threshold voltage and high breakdown voltage' [patent_app_type] => utility [patent_app_number] => 11/066492 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20050194648.pdf [firstpage_image] =>[orig_patent_app_number] => 11066492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066492
Semiconductor device including a transistor having low threshold voltage and high breakdown voltage Feb 27, 2005 Issued
Array ( [id] => 428926 [patent_doc_number] => 07268362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'High performance transistors with SiGe strain' [patent_app_type] => utility [patent_app_number] => 11/066062 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3868 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268362.pdf [firstpage_image] =>[orig_patent_app_number] => 11066062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066062
High performance transistors with SiGe strain Feb 24, 2005 Issued
Array ( [id] => 5098680 [patent_doc_number] => 20070181940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Trench field effect transistor and method of making it' [patent_app_type] => utility [patent_app_number] => 10/591192 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181940.pdf [firstpage_image] =>[orig_patent_app_number] => 10591192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/591192
Trench field effect transistor and method of making it Feb 22, 2005 Issued
Array ( [id] => 530049 [patent_doc_number] => 07183594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Configurable gate array cell with extended poly gate terminal' [patent_app_type] => utility [patent_app_number] => 11/058911 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3767 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183594.pdf [firstpage_image] =>[orig_patent_app_number] => 11058911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058911
Configurable gate array cell with extended poly gate terminal Feb 15, 2005 Issued
Array ( [id] => 7134649 [patent_doc_number] => 20050180189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Memory device electrode with a surface structure' [patent_app_type] => utility [patent_app_number] => 11/058412 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4158 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20050180189.pdf [firstpage_image] =>[orig_patent_app_number] => 11058412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058412
Memory device electrode with a surface structure Feb 15, 2005 Issued
Array ( [id] => 535311 [patent_doc_number] => 07180105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Normally off JFET' [patent_app_type] => utility [patent_app_number] => 11/053312 [patent_app_country] => US [patent_app_date] => 2005-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1378 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180105.pdf [firstpage_image] =>[orig_patent_app_number] => 11053312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053312
Normally off JFET Feb 7, 2005 Issued
Array ( [id] => 5670304 [patent_doc_number] => 20060175658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'High voltage laterally double-diffused metal oxide semiconductor' [patent_app_type] => utility [patent_app_number] => 11/050742 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4123 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20060175658.pdf [firstpage_image] =>[orig_patent_app_number] => 11050742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050742
High voltage laterally double-diffused metal oxide semiconductor Feb 6, 2005 Issued
Array ( [id] => 6975536 [patent_doc_number] => 20050285251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method of fabricating TFT array panel using aluminum wiring line and TFT array panel using the same method' [patent_app_type] => utility [patent_app_number] => 11/049742 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7706 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285251.pdf [firstpage_image] =>[orig_patent_app_number] => 11049742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049742
TFT array panel Feb 3, 2005 Issued
Array ( [id] => 620444 [patent_doc_number] => 07141861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Semiconductor device and manufacturing method there' [patent_app_type] => utility [patent_app_number] => 11/045581 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3334 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141861.pdf [firstpage_image] =>[orig_patent_app_number] => 11045581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/045581
Semiconductor device and manufacturing method there Jan 30, 2005 Issued
Array ( [id] => 513137 [patent_doc_number] => 07196383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Thin film oxide interface' [patent_app_type] => utility [patent_app_number] => 11/046571 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4690 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196383.pdf [firstpage_image] =>[orig_patent_app_number] => 11046571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046571
Thin film oxide interface Jan 27, 2005 Issued
Array ( [id] => 857301 [patent_doc_number] => 07375393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Non-volatile memory (NVM) retention improvement utilizing protective electrical shield' [patent_app_type] => utility [patent_app_number] => 11/044511 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2002 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375393.pdf [firstpage_image] =>[orig_patent_app_number] => 11044511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044511
Non-volatile memory (NVM) retention improvement utilizing protective electrical shield Jan 26, 2005 Issued
Array ( [id] => 5869044 [patent_doc_number] => 20060163661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Selective doping and thermal annealing method for forming a gate electrode pair with different work functions' [patent_app_type] => utility [patent_app_number] => 11/043621 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163661.pdf [firstpage_image] =>[orig_patent_app_number] => 11043621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/043621
Selective doping and thermal annealing method for forming a gate electrode pair with different work functions Jan 24, 2005 Issued
Array ( [id] => 5593790 [patent_doc_number] => 20060157706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Structure and method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels' [patent_app_type] => utility [patent_app_number] => 11/037622 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9108 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20060157706.pdf [firstpage_image] =>[orig_patent_app_number] => 11037622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037622
Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels Jan 17, 2005 Issued
Array ( [id] => 7094863 [patent_doc_number] => 20050127471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Semiconductor device having a dummy active region for controlling high density plasma chemical vapor deposition' [patent_app_type] => utility [patent_app_number] => 11/033829 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2831 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127471.pdf [firstpage_image] =>[orig_patent_app_number] => 11033829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033829
Semiconductor device having a dummy active region for controlling high density plasma chemical vapor deposition Jan 12, 2005 Abandoned
Array ( [id] => 7094788 [patent_doc_number] => 20050127431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Quantum structure and forming method of the same' [patent_app_type] => utility [patent_app_number] => 11/033862 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127431.pdf [firstpage_image] =>[orig_patent_app_number] => 11033862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033862
Quantum structure and forming method of the same Jan 12, 2005 Abandoned
Array ( [id] => 7178822 [patent_doc_number] => 20050124131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method of forming an inductor with continuous metal deposition' [patent_app_type] => utility [patent_app_number] => 11/034932 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2912 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124131.pdf [firstpage_image] =>[orig_patent_app_number] => 11034932 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034932
Method of forming an inductor with continuous metal deposition Jan 12, 2005 Abandoned
Array ( [id] => 7132968 [patent_doc_number] => 20050179112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Filling high aspect ratio isolation structures with polysilazane based material' [patent_app_type] => utility [patent_app_number] => 11/035392 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2159 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179112.pdf [firstpage_image] =>[orig_patent_app_number] => 11035392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035392
Filling high aspect ratio isolation structures with polysilazane based material Jan 11, 2005 Abandoned
Array ( [id] => 422115 [patent_doc_number] => 07274047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation' [patent_app_type] => utility [patent_app_number] => 11/032462 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17294 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274047.pdf [firstpage_image] =>[orig_patent_app_number] => 11032462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032462
Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation Jan 9, 2005 Issued
Array ( [id] => 721213 [patent_doc_number] => 07049650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/024422 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4861 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049650.pdf [firstpage_image] =>[orig_patent_app_number] => 11024422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024422
Semiconductor device Dec 29, 2004 Issued
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