Search

Paul A. Wartalowicz

Examiner (ID: 2067, Phone: (571)272-5957 , Office: P/1735 )

Most Active Art Unit
1735
Art Unit(s)
1735, 1754, 1793
Total Applications
1173
Issued Applications
607
Pending Applications
174
Abandoned Applications
411

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4382198 [patent_doc_number] => 06261974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Growth method of a polymer film' [patent_app_type] => 1 [patent_app_number] => 9/333875 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7547 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261974.pdf [firstpage_image] =>[orig_patent_app_number] => 333875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333875
Growth method of a polymer film Jun 13, 1999 Issued
Array ( [id] => 1486737 [patent_doc_number] => 06365938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-02 [patent_title] => 'Integrated circuit devices that use antiparallel diodes to reduce damage during plasma processing' [patent_app_type] => B2 [patent_app_number] => 09/333184 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4673 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365938.pdf [firstpage_image] =>[orig_patent_app_number] => 09333184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333184
Integrated circuit devices that use antiparallel diodes to reduce damage during plasma processing Jun 13, 1999 Issued
Array ( [id] => 4116933 [patent_doc_number] => 06071794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator' [patent_app_type] => 1 [patent_app_number] => 9/323746 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1090 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071794.pdf [firstpage_image] =>[orig_patent_app_number] => 323746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323746
Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator May 31, 1999 Issued
Array ( [id] => 4405770 [patent_doc_number] => 06232214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for fabricating inter-metal dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/316475 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1166 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232214.pdf [firstpage_image] =>[orig_patent_app_number] => 316475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316475
Method for fabricating inter-metal dielectric layer May 20, 1999 Issued
Array ( [id] => 4266147 [patent_doc_number] => 06259154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/294969 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 2682 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259154.pdf [firstpage_image] =>[orig_patent_app_number] => 294969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294969
Semiconductor device and method of manufacturing the same Apr 19, 1999 Issued
Array ( [id] => 4246301 [patent_doc_number] => 06136683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor device and method for production thereof' [patent_app_type] => 1 [patent_app_number] => 9/293944 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136683.pdf [firstpage_image] =>[orig_patent_app_number] => 293944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293944
Semiconductor device and method for production thereof Apr 18, 1999 Issued
Array ( [id] => 4408769 [patent_doc_number] => 06228722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method for fabricating self-aligned metal silcide' [patent_app_type] => 1 [patent_app_number] => 9/293433 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228722.pdf [firstpage_image] =>[orig_patent_app_number] => 293433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293433
Method for fabricating self-aligned metal silcide Apr 15, 1999 Issued
Array ( [id] => 4270274 [patent_doc_number] => 06245655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method for planarized deposition of a material' [patent_app_type] => 1 [patent_app_number] => 9/285162 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245655.pdf [firstpage_image] =>[orig_patent_app_number] => 285162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285162
Method for planarized deposition of a material Mar 31, 1999 Issued
Array ( [id] => 4270260 [patent_doc_number] => 06245654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method for preventing tungsten contact/via plug loss after a backside pressure fault' [patent_app_type] => 1 [patent_app_number] => 9/283063 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3532 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245654.pdf [firstpage_image] =>[orig_patent_app_number] => 283063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283063
Method for preventing tungsten contact/via plug loss after a backside pressure fault Mar 30, 1999 Issued
Array ( [id] => 4381764 [patent_doc_number] => 06294467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Process for forming fine wiring' [patent_app_type] => 1 [patent_app_number] => 9/270855 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6691 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294467.pdf [firstpage_image] =>[orig_patent_app_number] => 270855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270855
Process for forming fine wiring Mar 16, 1999 Issued
Array ( [id] => 7636597 [patent_doc_number] => 06380058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and apparatus for manufacturing semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/263942 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5277 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380058.pdf [firstpage_image] =>[orig_patent_app_number] => 09263942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263942
Method and apparatus for manufacturing semiconductor device Mar 7, 1999 Issued
Array ( [id] => 4407667 [patent_doc_number] => 06300144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method for fabricating ferro-electric thin films using a sol-gel technique' [patent_app_type] => 1 [patent_app_number] => 9/255916 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8079 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300144.pdf [firstpage_image] =>[orig_patent_app_number] => 255916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255916
Method for fabricating ferro-electric thin films using a sol-gel technique Feb 22, 1999 Issued
Array ( [id] => 1587749 [patent_doc_number] => 06359296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Circuit arrangement with at least one capacitor' [patent_app_type] => B1 [patent_app_number] => 09/250516 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359296.pdf [firstpage_image] =>[orig_patent_app_number] => 09250516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250516
Circuit arrangement with at least one capacitor Feb 15, 1999 Issued
Array ( [id] => 1594560 [patent_doc_number] => 06383915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect' [patent_app_type] => B1 [patent_app_number] => 09/244280 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9026 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383915.pdf [firstpage_image] =>[orig_patent_app_number] => 09244280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244280
Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect Feb 2, 1999 Issued
Array ( [id] => 4408004 [patent_doc_number] => 06309919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method for fabricating a trench-gated vertical CMOS device' [patent_app_type] => 1 [patent_app_number] => 9/237001 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309919.pdf [firstpage_image] =>[orig_patent_app_number] => 237001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237001
Method for fabricating a trench-gated vertical CMOS device Jan 24, 1999 Issued
Array ( [id] => 7636035 [patent_doc_number] => 06380625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-30 [patent_title] => 'Semiconductor interconnect barrier and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/229976 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380625.pdf [firstpage_image] =>[orig_patent_app_number] => 09229976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229976
Semiconductor interconnect barrier and manufacturing method thereof Jan 12, 1999 Issued
Array ( [id] => 4237846 [patent_doc_number] => 06090722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Process for fabricating a semiconductor structure having a self-aligned spacer' [patent_app_type] => 1 [patent_app_number] => 9/225595 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090722.pdf [firstpage_image] =>[orig_patent_app_number] => 225595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225595
Process for fabricating a semiconductor structure having a self-aligned spacer Jan 5, 1999 Issued
Array ( [id] => 4259265 [patent_doc_number] => 06204187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Contact and deep trench patterning' [patent_app_type] => 1 [patent_app_number] => 9/226434 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4027 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204187.pdf [firstpage_image] =>[orig_patent_app_number] => 226434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226434
Contact and deep trench patterning Jan 5, 1999 Issued
Array ( [id] => 1428368 [patent_doc_number] => 06504232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Integrated circuit components thereof and manufacturing method' [patent_app_type] => B2 [patent_app_number] => 09/224711 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5170 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504232.pdf [firstpage_image] =>[orig_patent_app_number] => 09224711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224711
Integrated circuit components thereof and manufacturing method Dec 30, 1998 Issued
Array ( [id] => 6686334 [patent_doc_number] => 20030030057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'SILICON CARBIDE DEPOSITION FOR USE AS A LOW-DIELECTRIC CONSTANT ANTI-REFLECTIVE COATING' [patent_app_type] => new [patent_app_number] => 09/219945 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10468 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20030030057.pdf [firstpage_image] =>[orig_patent_app_number] => 09219945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/219945
Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating Dec 22, 1998 Issued
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