Search

Paul A. Wartalowicz

Examiner (ID: 2067, Phone: (571)272-5957 , Office: P/1735 )

Most Active Art Unit
1735
Art Unit(s)
1735, 1754, 1793
Total Applications
1173
Issued Applications
607
Pending Applications
174
Abandoned Applications
411

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1399603 [patent_doc_number] => 06537920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Formation of vertical transistors using block copolymer lithography' [patent_app_type] => B1 [patent_app_number] => 09/809900 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537920.pdf [firstpage_image] =>[orig_patent_app_number] => 09809900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809900
Formation of vertical transistors using block copolymer lithography Mar 15, 2001 Issued
Array ( [id] => 1600133 [patent_doc_number] => 06475812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method for fabricating cladding layer in top conductor' [patent_app_type] => B2 [patent_app_number] => 09/802650 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2972 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475812.pdf [firstpage_image] =>[orig_patent_app_number] => 09802650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802650
Method for fabricating cladding layer in top conductor Mar 8, 2001 Issued
Array ( [id] => 1503567 [patent_doc_number] => 06465327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method for producing a thin membrane and resulting structure with membrane' [patent_app_type] => B1 [patent_app_number] => 09/763860 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4492 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465327.pdf [firstpage_image] =>[orig_patent_app_number] => 09763860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/763860
Method for producing a thin membrane and resulting structure with membrane Feb 27, 2001 Issued
Array ( [id] => 1382793 [patent_doc_number] => 06551945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Process for manufacturing a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/791220 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 8054 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551945.pdf [firstpage_image] =>[orig_patent_app_number] => 09791220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791220
Process for manufacturing a semiconductor device Feb 22, 2001 Issued
Array ( [id] => 6882695 [patent_doc_number] => 20010049167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Method of manufacturing a trench mosfet using selective growth epitaxy' [patent_app_type] => new [patent_app_number] => 09/780040 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049167.pdf [firstpage_image] =>[orig_patent_app_number] => 09780040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780040
Method of manufacturing a trench MOSFET using selective growth epitaxy Feb 8, 2001 Issued
Array ( [id] => 1559703 [patent_doc_number] => 06436765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of fabricating a trenched flash memory cell' [patent_app_type] => B1 [patent_app_number] => 09/779540 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2803 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436765.pdf [firstpage_image] =>[orig_patent_app_number] => 09779540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779540
Method of fabricating a trenched flash memory cell Feb 8, 2001 Issued
Array ( [id] => 6720429 [patent_doc_number] => 20030054117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Polymeric antireflective coatings deposited by plasma enhanced chemical vapor deposition' [patent_app_type] => new [patent_app_number] => 09/778980 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4568 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054117.pdf [firstpage_image] =>[orig_patent_app_number] => 09778980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778980
Polymeric antireflective coatings deposited by plasma enhanced chemical vapor deposition Feb 1, 2001 Abandoned
Array ( [id] => 1310268 [patent_doc_number] => 06613598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method for making a photovoltaic cell containing a dye' [patent_app_type] => B1 [patent_app_number] => 09/646843 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3914 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613598.pdf [firstpage_image] =>[orig_patent_app_number] => 09646843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/646843
Method for making a photovoltaic cell containing a dye Jan 28, 2001 Issued
Array ( [id] => 6016455 [patent_doc_number] => 20020102821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Mask pattern design to improve quality uniformity in lateral laser crystallized poly-Si films' [patent_app_type] => new [patent_app_number] => 09/774270 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3082 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102821.pdf [firstpage_image] =>[orig_patent_app_number] => 09774270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774270
Mask pattern design to improve quality uniformity in lateral laser crystallized poly-Si films Jan 28, 2001 Abandoned
Array ( [id] => 5828783 [patent_doc_number] => 20020068435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Method for removing carbon-rich particles adhered on the exposed copper surface of a copper/low k dielectric dual damascene structure' [patent_app_type] => new [patent_app_number] => 09/729201 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1631 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068435.pdf [firstpage_image] =>[orig_patent_app_number] => 09729201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729201
Method for removing carbon-rich particles adhered on the exposed copper surface of a copper/low k dielectric dual damascene structure Dec 4, 2000 Abandoned
Array ( [id] => 6095925 [patent_doc_number] => 20020052098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method of fabricating gate' [patent_app_type] => new [patent_app_number] => 09/726460 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3384 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052098.pdf [firstpage_image] =>[orig_patent_app_number] => 09726460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726460
Method of fabricating gate Nov 29, 2000 Issued
Array ( [id] => 6900124 [patent_doc_number] => 20010009800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Manufacture of trench-gate semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/725410 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5166 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009800.pdf [firstpage_image] =>[orig_patent_app_number] => 09725410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725410
Manufacture of trench-gate semiconductor devices Nov 28, 2000 Issued
Array ( [id] => 1595606 [patent_doc_number] => 06492247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/717970 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4997 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492247.pdf [firstpage_image] =>[orig_patent_app_number] => 09717970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717970
Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits Nov 20, 2000 Issued
Array ( [id] => 1469840 [patent_doc_number] => 06406978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method of removing silicon carbide' [patent_app_type] => B1 [patent_app_number] => 09/715420 [patent_app_country] => US [patent_app_date] => 2000-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406978.pdf [firstpage_image] =>[orig_patent_app_number] => 09715420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715420
Method of removing silicon carbide Nov 17, 2000 Issued
Array ( [id] => 1588789 [patent_doc_number] => 06482697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method of forming a highly integrated non-volatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/705880 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12640 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482697.pdf [firstpage_image] =>[orig_patent_app_number] => 09705880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705880
Method of forming a highly integrated non-volatile semiconductor memory device Nov 5, 2000 Issued
Array ( [id] => 1523607 [patent_doc_number] => 06352877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Metal layer in semiconductor device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/696200 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352877.pdf [firstpage_image] =>[orig_patent_app_number] => 09696200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696200
Metal layer in semiconductor device and method for fabricating the same Oct 25, 2000 Issued
Array ( [id] => 1347560 [patent_doc_number] => 06579802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method of forming smooth morphologies in InP-based semiconductors' [patent_app_type] => B1 [patent_app_number] => 09/672411 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3372 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579802.pdf [firstpage_image] =>[orig_patent_app_number] => 09672411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672411
Method of forming smooth morphologies in InP-based semiconductors Sep 27, 2000 Issued
Array ( [id] => 1419065 [patent_doc_number] => 06506646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method for manufacturing a semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/671211 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 4266 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506646.pdf [firstpage_image] =>[orig_patent_app_number] => 09671211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671211
Method for manufacturing a semiconductor memory Sep 27, 2000 Issued
Array ( [id] => 1565909 [patent_doc_number] => 06376342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of forming a metal silicide layer on a source/drain region of a MOSFET device' [patent_app_type] => B1 [patent_app_number] => 09/671511 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1842 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376342.pdf [firstpage_image] =>[orig_patent_app_number] => 09671511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671511
Method of forming a metal silicide layer on a source/drain region of a MOSFET device Sep 26, 2000 Issued
Array ( [id] => 1411862 [patent_doc_number] => 06524899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Process for forming a large area, high gate current HEMT diode' [patent_app_type] => B1 [patent_app_number] => 09/667360 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2243 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524899.pdf [firstpage_image] =>[orig_patent_app_number] => 09667360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667360
Process for forming a large area, high gate current HEMT diode Sep 20, 2000 Issued
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