Search

Paul A. Wartalowicz

Examiner (ID: 2067, Phone: (571)272-5957 , Office: P/1735 )

Most Active Art Unit
1735
Art Unit(s)
1735, 1754, 1793
Total Applications
1173
Issued Applications
607
Pending Applications
174
Abandoned Applications
411

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1474697 [patent_doc_number] => 06387820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'BC13/AR chemistry for metal overetching on a high density plasma etcher' [patent_app_type] => B1 [patent_app_number] => 09/664950 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2606 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387820.pdf [firstpage_image] =>[orig_patent_app_number] => 09664950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664950
BC13/AR chemistry for metal overetching on a high density plasma etcher Sep 18, 2000 Issued
Array ( [id] => 7631345 [patent_doc_number] => 06635587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method for producing czochralski silicon free of agglomerated self-interstitial defects' [patent_app_type] => B1 [patent_app_number] => 09/661821 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4607 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635587.pdf [firstpage_image] =>[orig_patent_app_number] => 09661821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661821
Method for producing czochralski silicon free of agglomerated self-interstitial defects Sep 13, 2000 Issued
Array ( [id] => 1595573 [patent_doc_number] => 06492240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method for forming improved high resistance resistor by treating the surface of polysilicon layer' [patent_app_type] => B1 [patent_app_number] => 09/661701 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 2618 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492240.pdf [firstpage_image] =>[orig_patent_app_number] => 09661701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661701
Method for forming improved high resistance resistor by treating the surface of polysilicon layer Sep 13, 2000 Issued
Array ( [id] => 1561864 [patent_doc_number] => 06437435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Vertically mountable interposer, assembly and method' [patent_app_type] => B1 [patent_app_number] => 09/651491 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 26 [patent_no_of_words] => 4187 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437435.pdf [firstpage_image] =>[orig_patent_app_number] => 09651491 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651491
Vertically mountable interposer, assembly and method Aug 29, 2000 Issued
Array ( [id] => 7636582 [patent_doc_number] => 06380073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method for forming metal interconnection structure without corner faceted' [patent_app_type] => B1 [patent_app_number] => 09/650910 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 2650 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380073.pdf [firstpage_image] =>[orig_patent_app_number] => 09650910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650910
Method for forming metal interconnection structure without corner faceted Aug 28, 2000 Issued
Array ( [id] => 1371188 [patent_doc_number] => 06562657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint' [patent_app_type] => B1 [patent_app_number] => 09/643214 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 8648 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562657.pdf [firstpage_image] =>[orig_patent_app_number] => 09643214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643214
Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint Aug 21, 2000 Issued
Array ( [id] => 1500538 [patent_doc_number] => 06486078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Super critical drying of low k materials' [patent_app_type] => B1 [patent_app_number] => 09/643531 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486078.pdf [firstpage_image] =>[orig_patent_app_number] => 09643531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643531
Super critical drying of low k materials Aug 21, 2000 Issued
Array ( [id] => 1264488 [patent_doc_number] => 06660618 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems' [patent_app_type] => B1 [patent_app_number] => 09/640080 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 5982 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660618.pdf [firstpage_image] =>[orig_patent_app_number] => 09640080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640080
Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Aug 16, 2000 Issued
09/638410 Use of sub-melt laser annealing and low temperature rapid thermal annealing to form ultrashallow junctions in semiconductor wafers Aug 10, 2000 Abandoned
Array ( [id] => 1382183 [patent_doc_number] => 06551909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Semiconductor device with alternating conductivity type layer and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/629711 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 9411 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551909.pdf [firstpage_image] =>[orig_patent_app_number] => 09629711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629711
Semiconductor device with alternating conductivity type layer and method of manufacturing the same Jul 30, 2000 Issued
Array ( [id] => 7643977 [patent_doc_number] => 06429061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation' [patent_app_type] => B1 [patent_app_number] => 09/626331 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2338 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429061.pdf [firstpage_image] =>[orig_patent_app_number] => 09626331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626331
Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation Jul 25, 2000 Issued
Array ( [id] => 1347319 [patent_doc_number] => 06579781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Elimination of n contact implant from flash technologies by replacement with standard double-diffused and n implants' [patent_app_type] => B1 [patent_app_number] => 09/619231 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 66 [patent_no_of_words] => 3606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579781.pdf [firstpage_image] =>[orig_patent_app_number] => 09619231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619231
Elimination of n contact implant from flash technologies by replacement with standard double-diffused and n implants Jul 18, 2000 Issued
Array ( [id] => 1519089 [patent_doc_number] => 06501180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures' [patent_app_type] => B1 [patent_app_number] => 09/619351 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2466 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501180.pdf [firstpage_image] =>[orig_patent_app_number] => 09619351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619351
Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures Jul 18, 2000 Issued
Array ( [id] => 1532355 [patent_doc_number] => 06410364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment' [patent_app_type] => B1 [patent_app_number] => 09/555141 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6001 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410364.pdf [firstpage_image] =>[orig_patent_app_number] => 09555141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/555141
Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment May 24, 2000 Issued
Array ( [id] => 1419444 [patent_doc_number] => 06506678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same' [patent_app_type] => B1 [patent_app_number] => 09/574771 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5543 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506678.pdf [firstpage_image] =>[orig_patent_app_number] => 09574771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574771
Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same May 18, 2000 Issued
Array ( [id] => 1523778 [patent_doc_number] => 06352932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Methods of forming integrated circuitry and integrated circuitry structures' [patent_app_type] => B1 [patent_app_number] => 09/550401 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 3337 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352932.pdf [firstpage_image] =>[orig_patent_app_number] => 09550401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550401
Methods of forming integrated circuitry and integrated circuitry structures Apr 13, 2000 Issued
Array ( [id] => 1264676 [patent_doc_number] => 06660664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Structure and method for formation of a blocked silicide resistor' [patent_app_type] => B1 [patent_app_number] => 09/541091 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7488 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660664.pdf [firstpage_image] =>[orig_patent_app_number] => 09541091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541091
Structure and method for formation of a blocked silicide resistor Mar 30, 2000 Issued
Array ( [id] => 1416800 [patent_doc_number] => 06509264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method to form self-aligned silicide with reduced sheet resistance' [patent_app_type] => B1 [patent_app_number] => 09/537480 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509264.pdf [firstpage_image] =>[orig_patent_app_number] => 09537480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537480
Method to form self-aligned silicide with reduced sheet resistance Mar 29, 2000 Issued
Array ( [id] => 1297642 [patent_doc_number] => 06627554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/537430 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 58 [patent_no_of_words] => 11162 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627554.pdf [firstpage_image] =>[orig_patent_app_number] => 09537430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537430
Semiconductor device manufacturing method Mar 26, 2000 Issued
Array ( [id] => 1490209 [patent_doc_number] => 06417069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Substrate processing method and manufacturing method, and anodizing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/532071 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 18513 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417069.pdf [firstpage_image] =>[orig_patent_app_number] => 09532071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532071
Substrate processing method and manufacturing method, and anodizing apparatus Mar 20, 2000 Issued
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