Paul A. Wartalowicz

Array ( [id] => 4289326 [patent_doc_number] => 06235564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of manufacturing MISFET' [patent_app_type] => 1 [patent_app_number] => 9/487620 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 51 [patent_no_of_words] => 8679 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235564.pdf [firstpage_image] =>[orig_patent_app_number] => 487620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7014574 [patent_doc_number] => 20010051420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch' [patent_app_type] => new [patent_app_number] => 09/487531 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7327 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051420.pdf [firstpage_image] =>[orig_patent_app_number] => 09487531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559829 [patent_doc_number] => 06436807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for making an interconnect layer and a semiconductor device including the same' [patent_app_type] => B1 [patent_app_number] => 09/484310 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3304 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436807.pdf [firstpage_image] =>[orig_patent_app_number] => 09484310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303564 [patent_doc_number] => 06326252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for fabricating MOS transistor having dual gate' [patent_app_type] => 1 [patent_app_number] => 9/481321 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 2902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326252.pdf [firstpage_image] =>[orig_patent_app_number] => 481321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6224733 [patent_doc_number] => 20020004305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Semiconductor Wafer Manufacturing Process' [patent_app_type] => new [patent_app_number] => 09/481080 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6575 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004305.pdf [firstpage_image] =>[orig_patent_app_number] => 09481080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523563 [patent_doc_number] => 06352867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of controlling feature dimensions based upon etch chemistry concentrations' [patent_app_type] => B1 [patent_app_number] => 09/478181 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4002 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352867.pdf [firstpage_image] =>[orig_patent_app_number] => 09478181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1235777 [patent_doc_number] => 06689689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Selective deposition process for allowing damascene-type Cu interconnect lines' [patent_app_type] => B1 [patent_app_number] => 09/477821 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689689.pdf [firstpage_image] =>[orig_patent_app_number] => 09477821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4285959 [patent_doc_number] => 06211018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for fabricating high density trench gate type power device' [patent_app_type] => 1 [patent_app_number] => 9/475281 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 4324 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211018.pdf [firstpage_image] =>[orig_patent_app_number] => 475281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236143 [patent_doc_number] => 06165911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method of patterning a metal layer' [patent_app_type] => 1 [patent_app_number] => 9/474420 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165911.pdf [firstpage_image] =>[orig_patent_app_number] => 474420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368448 [patent_doc_number] => 06287899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/474070 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 67 [patent_no_of_words] => 15636 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287899.pdf [firstpage_image] =>[orig_patent_app_number] => 474070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156600 [patent_doc_number] => 06156669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method of patterning a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/471215 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3049 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156669.pdf [firstpage_image] =>[orig_patent_app_number] => 471215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1397139 [patent_doc_number] => 06531389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method for forming incompletely landed via with attenuated contact resistance' [patent_app_type] => B1 [patent_app_number] => 09/467130 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7264 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531389.pdf [firstpage_image] =>[orig_patent_app_number] => 09467130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1542775 [patent_doc_number] => 06372647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Via masked line first dual damascene' [patent_app_type] => B1 [patent_app_number] => 09/460870 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2096 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372647.pdf [firstpage_image] =>[orig_patent_app_number] => 09460870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1494201 [patent_doc_number] => 06342412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/459921 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 112 [patent_no_of_words] => 56016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342412.pdf [firstpage_image] =>[orig_patent_app_number] => 09459921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7064939 [patent_doc_number] => 20010044176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'MANUFACTURING PROCESS OF A HIGH INTEGRATION DENSITY POWER MOS DEVICE' [patent_app_type] => new [patent_app_number] => 09/457070 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2287 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044176.pdf [firstpage_image] =>[orig_patent_app_number] => 09457070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404911 [patent_doc_number] => 06232141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor light-receiving device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/455771 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5833 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232141.pdf [firstpage_image] =>[orig_patent_app_number] => 455771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293933 [patent_doc_number] => 06197663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Process for fabricating integrated circuit devices having thin film transistors' [patent_app_type] => 1 [patent_app_number] => 9/456210 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3735 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197663.pdf [firstpage_image] =>[orig_patent_app_number] => 456210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138165 [patent_doc_number] => 06780704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Conformal thin films over textured capacitor electrodes' [patent_app_type] => B1 [patent_app_number] => 09/452844 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14286 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780704.pdf [firstpage_image] =>[orig_patent_app_number] => 09452844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405094 [patent_doc_number] => 06232155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Methods of fabricating semiconductor-on-insulator devices including alternating thin and thick film semiconductor regions on an insulating layer' [patent_app_type] => 1 [patent_app_number] => 9/454340 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3419 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232155.pdf [firstpage_image] =>[orig_patent_app_number] => 454340 [rel_patent_id] =>[rel_patent_doc_number] =>)