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Paul Alvare

Examiner (ID: 6865)

Most Active Art Unit
3763
Art Unit(s)
3763, 3744
Total Applications
697
Issued Applications
343
Pending Applications
90
Abandoned Applications
282

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17032833 [patent_doc_number] => 11094651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/856805 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856805
Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture Apr 22, 2020 Issued
Array ( [id] => 17032833 [patent_doc_number] => 11094651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/856805 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856805
Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture Apr 22, 2020 Issued
Array ( [id] => 17032833 [patent_doc_number] => 11094651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/856805 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856805
Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture Apr 22, 2020 Issued
Array ( [id] => 17032833 [patent_doc_number] => 11094651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/856805 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856805
Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture Apr 22, 2020 Issued
Array ( [id] => 16896351 [patent_doc_number] => 11037913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/854971 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6936 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854971
Semiconductor package Apr 21, 2020 Issued
Array ( [id] => 16226323 [patent_doc_number] => 20200251440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => INTEGRATED CIRCUIT PACKAGING [patent_app_type] => utility [patent_app_number] => 16/854823 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854823
Integrated circuit packaging Apr 20, 2020 Issued
Array ( [id] => 16881147 [patent_doc_number] => 11031304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/853024 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853024
Method of manufacturing semiconductor device Apr 19, 2020 Issued
Array ( [id] => 16528891 [patent_doc_number] => 20200402972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/851978 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851978
Semiconductor device and method of manufacturing the same Apr 16, 2020 Issued
Array ( [id] => 16716054 [patent_doc_number] => 20210083201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/850208 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 1073 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850208 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/850208
Heterocyclic compound and organic light-emitting device including the same Apr 15, 2020 Issued
Array ( [id] => 17016540 [patent_doc_number] => 11086175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Display device and electronic appliance [patent_app_type] => utility [patent_app_number] => 16/846519 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 19343 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846519 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846519
Display device and electronic appliance Apr 12, 2020 Issued
Array ( [id] => 16455811 [patent_doc_number] => 20200365237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => Stable Label Isotope Tracing for Untargeted Data [patent_app_type] => utility [patent_app_number] => 16/846185 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846185
Stable label isotope tracing for untargeted data Apr 9, 2020 Issued
Array ( [id] => 16988108 [patent_doc_number] => 11075291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => Isolation structure for IGBT devices having an integrated diode [patent_app_type] => utility [patent_app_number] => 16/844159 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844159
Isolation structure for IGBT devices having an integrated diode Apr 8, 2020 Issued
Array ( [id] => 16866071 [patent_doc_number] => 11024826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Display substrate [patent_app_type] => utility [patent_app_number] => 16/843198 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843198
Display substrate Apr 7, 2020 Issued
Array ( [id] => 16835114 [patent_doc_number] => 11011373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Engineered substrate structures for power and RF applications [patent_app_type] => utility [patent_app_number] => 16/837817 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837817
Engineered substrate structures for power and RF applications Mar 31, 2020 Issued
Array ( [id] => 16987927 [patent_doc_number] => 11075110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => Transistor trench with field plate structure [patent_app_type] => utility [patent_app_number] => 16/836293 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 5555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836293
Transistor trench with field plate structure Mar 30, 2020 Issued
Array ( [id] => 17284050 [patent_doc_number] => 11201091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor structure implementing series-connected transistor and resistor and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/834673 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8490 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834673
Semiconductor structure implementing series-connected transistor and resistor and method for forming the same Mar 29, 2020 Issued
Array ( [id] => 17424409 [patent_doc_number] => 11257872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Display panel and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/753185 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4467 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16753185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/753185
Display panel and manufacturing method thereof Mar 5, 2020 Issued
Array ( [id] => 17224776 [patent_doc_number] => 11177286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Integrated circuit device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/807410 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 11544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807410
Integrated circuit device and method of manufacturing the same Mar 2, 2020 Issued
Array ( [id] => 18371658 [patent_doc_number] => 11651839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Systems and methods for generating phase diagrams for metastable material states [patent_app_type] => utility [patent_app_number] => 16/807081 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7928 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807081 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807081
Systems and methods for generating phase diagrams for metastable material states Mar 1, 2020 Issued
Array ( [id] => 17803298 [patent_doc_number] => 11417611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Devices and methods for reducing stress on circuit components [patent_app_type] => utility [patent_app_number] => 16/801093 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 6085 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801093 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801093
Devices and methods for reducing stress on circuit components Feb 24, 2020 Issued
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