Search

Paul B. Yanchus Iii

Examiner (ID: 7899, Phone: (571)272-3678 , Office: P/2116 )

Most Active Art Unit
2116
Art Unit(s)
2115, 2127, 2119, 2185, 2116
Total Applications
1110
Issued Applications
881
Pending Applications
78
Abandoned Applications
167

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10363509 [patent_doc_number] => 20150248514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'AUTOMATIC LAYOUT MODIFICATION TOOL WITH NON-UNIFORM GRIDS' [patent_app_type] => utility [patent_app_number] => 14/629303 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10120 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629303
Automatic layout modification tool with non-uniform grids Feb 22, 2015 Issued
Array ( [id] => 11049952 [patent_doc_number] => 20160246910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Memory Optimization in VLSI Design Using Generic Memory Models' [patent_app_type] => utility [patent_app_number] => 14/628105 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628105
Memory optimization in VLSI design using generic memory models Feb 19, 2015 Issued
Array ( [id] => 11709282 [patent_doc_number] => 20170177782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'CLASSICAL SIMULATION CONSTANTS AND ORDERING FOR QUANTUM CHEMISTRY SIMULATION' [patent_app_type] => utility [patent_app_number] => 15/118476 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5076 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15118476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/118476
Classical simulation constants and ordering for quantum chemistry simulation Feb 5, 2015 Issued
Array ( [id] => 12256185 [patent_doc_number] => 09928331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method and control device for circuit layout migration' [patent_app_type] => utility [patent_app_number] => 14/561280 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561280
Method and control device for circuit layout migration Dec 4, 2014 Issued
Array ( [id] => 14615259 [patent_doc_number] => 10360332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Handling blind statements in mixed language environments [patent_app_type] => utility [patent_app_number] => 14/549242 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549242 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549242
Handling blind statements in mixed language environments Nov 19, 2014 Issued
Array ( [id] => 10702481 [patent_doc_number] => 20160048628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD FOR DYNAMIC EXPERIMENTAL DESIGN' [patent_app_type] => utility [patent_app_number] => 14/547731 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547731 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547731
METHOD FOR DYNAMIC EXPERIMENTAL DESIGN Nov 18, 2014 Abandoned
Array ( [id] => 9919424 [patent_doc_number] => 20150074629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/542690 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542690
Parasitic component library and method for efficient circuit design and simulation using the same Nov 16, 2014 Issued
Array ( [id] => 10105965 [patent_doc_number] => 09141747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-22 [patent_title] => 'System level tools to support FPGA partial reconfiguration' [patent_app_type] => utility [patent_app_number] => 14/538697 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6447 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538697
System level tools to support FPGA partial reconfiguration Nov 10, 2014 Issued
Array ( [id] => 10786471 [patent_doc_number] => 20160132627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'METHOD AND SYSTEM TO PREPARE, MANUFACTURE AND INSPECT MASK PATTERNS FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/536031 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536031
Method and system to prepare, manufacture and inspect mask patterns for a semiconductor device Nov 6, 2014 Issued
Array ( [id] => 10786470 [patent_doc_number] => 20160132626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'METHOD OF DECOMPOSING LAYOUT DESIGN FOR PREPARING PHOTOMASK SET PRINTED ONTO WAFER BY PHOTOLITHOGRAPHY, METHOD OF FORMING PHOTOMASK SET AND METHOD OF FABRICATING INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/534190 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534190 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/534190
Method of decomposing layout design for preparing photomask set printed onto wafer by photolithography, method of forming photomask set and method of fabricating integrated circuit Nov 5, 2014 Issued
Array ( [id] => 10778959 [patent_doc_number] => 20160125115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'GENERATING AN ELECTROMAGNETIC PARAMETERIZED CELL FOR AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/533148 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533148 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533148
GENERATING AN ELECTROMAGNETIC PARAMETERIZED CELL FOR AN INTEGRATED CIRCUIT DESIGN Nov 4, 2014 Abandoned
Array ( [id] => 10778958 [patent_doc_number] => 20160125114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'METHOD AND APPARATUS FOR BITCELL MODELING' [patent_app_type] => utility [patent_app_number] => 14/531451 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531451 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531451
Method and apparatus for bitcell modeling Nov 2, 2014 Issued
Array ( [id] => 14604625 [patent_doc_number] => 10355511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Mobile-terminal charging device and vehicle equipped with same [patent_app_type] => utility [patent_app_number] => 15/027729 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7134 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15027729 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/027729
Mobile-terminal charging device and vehicle equipped with same Oct 29, 2014 Issued
Array ( [id] => 11411006 [patent_doc_number] => 09558311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Surface region selection for heat sink placement' [patent_app_type] => utility [patent_app_number] => 14/525292 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9819 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525292
Surface region selection for heat sink placement Oct 27, 2014 Issued
Array ( [id] => 10432414 [patent_doc_number] => 20150317426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'DATA PATH SYSTEM ON CHIP DESIGN METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 14/498939 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8894 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498939
DATA PATH SYSTEM ON CHIP DESIGN METHODOLOGY Sep 25, 2014 Abandoned
Array ( [id] => 11473421 [patent_doc_number] => 20170060204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC' [patent_app_type] => utility [patent_app_number] => 14/498907 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498907 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498907
Automatic generation of power management sequence in a SoC or NoC Sep 25, 2014 Issued
Array ( [id] => 10210879 [patent_doc_number] => 20150095871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/497876 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 11288 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497876 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/497876
CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT Sep 25, 2014 Abandoned
Array ( [id] => 10210873 [patent_doc_number] => 20150095865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'Legalizing a Multi-patterning Integrated Circuit Layout' [patent_app_type] => utility [patent_app_number] => 14/498663 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8626 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498663 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498663
Legalizing a multi-patterning integrated circuit layout Sep 25, 2014 Issued
Array ( [id] => 11046999 [patent_doc_number] => 20160243957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'METHOD FOR MINIMIZING CELL AGING OF A BATTERY AND/OR BATTERY COMPRISING AN APPARATUS FOR MINIMIZING CELL AGING OF THE BATTERY' [patent_app_type] => utility [patent_app_number] => 15/027553 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3434 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15027553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/027553
Method for minimizing cell aging of a battery and/or battery comprising an apparatus for minimizing cell aging of the battery Sep 24, 2014 Issued
Array ( [id] => 10105972 [patent_doc_number] => 09141754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Generating a semiconductor component layout' [patent_app_type] => utility [patent_app_number] => 14/489155 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489155
Generating a semiconductor component layout Sep 16, 2014 Issued
Menu