
Paul B. Yanchus Iii
Examiner (ID: 7899, Phone: (571)272-3678 , Office: P/2116 )
| Most Active Art Unit | 2116 |
| Art Unit(s) | 2115, 2127, 2119, 2185, 2116 |
| Total Applications | 1110 |
| Issued Applications | 881 |
| Pending Applications | 78 |
| Abandoned Applications | 167 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10363509
[patent_doc_number] => 20150248514
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[patent_title] => 'AUTOMATIC LAYOUT MODIFICATION TOOL WITH NON-UNIFORM GRIDS'
[patent_app_type] => utility
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Array
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[patent_kind] => A1
[patent_issue_date] => 2016-08-25
[patent_title] => 'Memory Optimization in VLSI Design Using Generic Memory Models'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2017-06-22
[patent_title] => 'CLASSICAL SIMULATION CONSTANTS AND ORDERING FOR QUANTUM CHEMISTRY SIMULATION'
[patent_app_type] => utility
[patent_app_number] => 15/118476
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Array
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[patent_title] => 'Method and control device for circuit layout migration'
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Array
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[patent_title] => Handling blind statements in mixed language environments
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Array
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[patent_title] => 'METHOD FOR DYNAMIC EXPERIMENTAL DESIGN'
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Array
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[patent_title] => 'PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/542690 | Parasitic component library and method for efficient circuit design and simulation using the same | Nov 16, 2014 | Issued |
Array
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[patent_title] => 'System level tools to support FPGA partial reconfiguration'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/538697 | System level tools to support FPGA partial reconfiguration | Nov 10, 2014 | Issued |
Array
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[id] => 10786471
[patent_doc_number] => 20160132627
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[patent_issue_date] => 2016-05-12
[patent_title] => 'METHOD AND SYSTEM TO PREPARE, MANUFACTURE AND INSPECT MASK PATTERNS FOR A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/536031
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/536031 | Method and system to prepare, manufacture and inspect mask patterns for a semiconductor device | Nov 6, 2014 | Issued |
Array
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[patent_title] => 'METHOD OF DECOMPOSING LAYOUT DESIGN FOR PREPARING PHOTOMASK SET PRINTED ONTO WAFER BY PHOTOLITHOGRAPHY, METHOD OF FORMING PHOTOMASK SET AND METHOD OF FABRICATING INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 14/534190
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/534190 | Method of decomposing layout design for preparing photomask set printed onto wafer by photolithography, method of forming photomask set and method of fabricating integrated circuit | Nov 5, 2014 | Issued |
Array
(
[id] => 10778959
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[patent_title] => 'GENERATING AN ELECTROMAGNETIC PARAMETERIZED CELL FOR AN INTEGRATED CIRCUIT DESIGN'
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[patent_app_number] => 14/533148
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Array
(
[id] => 10778958
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[patent_title] => 'METHOD AND APPARATUS FOR BITCELL MODELING'
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Array
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Array
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Array
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Array
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Array
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