Search

Paul B. Yanchus Iii

Examiner (ID: 7899, Phone: (571)272-3678 , Office: P/2116 )

Most Active Art Unit
2116
Art Unit(s)
2115, 2127, 2119, 2185, 2116
Total Applications
1110
Issued Applications
881
Pending Applications
78
Abandoned Applications
167

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11637158 [patent_doc_number] => 09659133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Method, system and computer program product for generating layout for semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/056420 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 8687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056420
Method, system and computer program product for generating layout for semiconductor device Oct 16, 2013 Issued
Array ( [id] => 11179930 [patent_doc_number] => 09411924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Methodology for pattern density optimization' [patent_app_type] => utility [patent_app_number] => 14/051549 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051549 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051549
Methodology for pattern density optimization Oct 10, 2013 Issued
Array ( [id] => 9980625 [patent_doc_number] => 09026956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Method of lithographic process evaluation' [patent_app_type] => utility [patent_app_number] => 14/051640 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051640 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051640
Method of lithographic process evaluation Oct 10, 2013 Issued
Array ( [id] => 9781492 [patent_doc_number] => 08856716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Automatic placement system of IC design and method thereof' [patent_app_type] => utility [patent_app_number] => 14/027830 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6195 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027830 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/027830
Automatic placement system of IC design and method thereof Sep 15, 2013 Issued
Array ( [id] => 11346791 [patent_doc_number] => 09531208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Charging and communicating with battery operated toys' [patent_app_type] => utility [patent_app_number] => 14/026196 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14026196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/026196
Charging and communicating with battery operated toys Sep 12, 2013 Issued
Array ( [id] => 9381377 [patent_doc_number] => 20140084858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'WIRELESS POWER TRANSMISSION APPARATUS AND METHOD AND WIRELESS POWER RECEPTION APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/025516 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/025516
Wireless power transmission apparatus and method and wireless power reception apparatus Sep 11, 2013 Issued
Array ( [id] => 11563576 [patent_doc_number] => 09626165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language' [patent_app_type] => utility [patent_app_number] => 14/024860 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6758 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024860 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024860
Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language Sep 11, 2013 Issued
Array ( [id] => 9632305 [patent_doc_number] => 20140210413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'CHARGING AND DISCHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/025790 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6147 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/025790
Charging and discharging system Sep 11, 2013 Issued
Array ( [id] => 10584313 [patent_doc_number] => 09306443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Analog photovoltaic power circuit with auto zero calibration' [patent_app_type] => utility [patent_app_number] => 14/023900 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 9960 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023900
Analog photovoltaic power circuit with auto zero calibration Sep 10, 2013 Issued
Array ( [id] => 9566448 [patent_doc_number] => 20140184161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SOLID-STATE ACTIVE SWITCH MATRIX FOR HIGH ENERGY, MODERATE POWER BATTERY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/023394 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023394
Solid-state active switch matrix for high energy, moderate power battery systems Sep 9, 2013 Issued
Array ( [id] => 9860073 [patent_doc_number] => 20150040090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/016010 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016010 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016010
Discretizing gate sizes during numerical synthesis Aug 29, 2013 Issued
Array ( [id] => 11245748 [patent_doc_number] => 09471792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Detection arrangement' [patent_app_type] => utility [patent_app_number] => 14/010145 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010145
Detection arrangement Aug 25, 2013 Issued
Array ( [id] => 9623437 [patent_doc_number] => 08793633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-29 [patent_title] => 'In-hierarchy circuit analysis and modification' [patent_app_type] => utility [patent_app_number] => 13/971666 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3936 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971666
In-hierarchy circuit analysis and modification Aug 19, 2013 Issued
Array ( [id] => 9332721 [patent_doc_number] => 20140059503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'METHOD FOR PREPARING A PATTERN TO BE PRINTED ON A PLATE OR MASK BY ELECTRON BEAM LITHOGRAPHY, CORRESPONDING PRINTED CIRCUIT DESIGN SYSTEM AND COMPUTER PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/967740 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967740
Method and system for preparing a pattern to be printed on a plate or mask by electron beam lithography Aug 14, 2013 Issued
Array ( [id] => 10885704 [patent_doc_number] => 08910109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'System level tools to support FPGA partial reconfiguration' [patent_app_type] => utility [patent_app_number] => 13/964430 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964430 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964430
System level tools to support FPGA partial reconfiguration Aug 11, 2013 Issued
Array ( [id] => 9386399 [patent_doc_number] => 20140089882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR MODULARIZING POWER SUPPLIES PLACED ON PCB' [patent_app_type] => utility [patent_app_number] => 13/961889 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1746 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13961889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/961889
COMPUTING DEVICE AND METHOD FOR MODULARIZING POWER SUPPLIES PLACED ON PCB Aug 7, 2013 Abandoned
Array ( [id] => 9372700 [patent_doc_number] => 20140082573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/953309 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7349 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953309 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953309
CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT Jul 28, 2013 Abandoned
Array ( [id] => 11550753 [patent_doc_number] => 09619605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects' [patent_app_type] => utility [patent_app_number] => 13/949549 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11711 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949549
System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects Jul 23, 2013 Issued
Array ( [id] => 13639597 [patent_doc_number] => 09846758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Method of designing an integrated circuit and computer program product [patent_app_type] => utility [patent_app_number] => 14/899280 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4230 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899280
Method of designing an integrated circuit and computer program product Jul 22, 2013 Issued
Array ( [id] => 10623700 [patent_doc_number] => 09342643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method' [patent_app_type] => utility [patent_app_number] => 13/946859 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946859
Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method Jul 18, 2013 Issued
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