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Paul Bowen

Examiner (ID: 4672)

Most Active Art Unit
2405
Art Unit(s)
2405
Total Applications
308
Issued Applications
222
Pending Applications
2
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16354748 [patent_doc_number] => 10795255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method of forming layout definition of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/175858 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4103 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175858
Method of forming layout definition of semiconductor device Oct 30, 2018 Issued
Array ( [id] => 15840527 [patent_doc_number] => 20200135546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Method for Shrinking Openings in Forming Integrated Circuits [patent_app_type] => utility [patent_app_number] => 16/176116 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176116
Method for shrinking openings in forming integrated circuits Oct 30, 2018 Issued
Array ( [id] => 15840413 [patent_doc_number] => 20200135489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN [patent_app_type] => utility [patent_app_number] => 16/176005 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176005
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN Oct 30, 2018 Pending
Array ( [id] => 18152412 [patent_doc_number] => 11565365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => System and method for monitoring chemical mechanical polishing [patent_app_type] => utility [patent_app_number] => 16/175778 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175778
System and method for monitoring chemical mechanical polishing Oct 29, 2018 Issued
Array ( [id] => 15841231 [patent_doc_number] => 20200135898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => HARD MASK REPLENISHMENT FOR ETCHING PROCESSES [patent_app_type] => utility [patent_app_number] => 16/175032 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175032
HARD MASK REPLENISHMENT FOR ETCHING PROCESSES Oct 29, 2018 Abandoned
Array ( [id] => 15840363 [patent_doc_number] => 20200135464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHODS AND APPARATUS FOR PATTERNING SUBSTRATES USING ASYMMETRIC PHYSICAL VAPOR DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/175289 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175289 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175289
METHODS AND APPARATUS FOR PATTERNING SUBSTRATES USING ASYMMETRIC PHYSICAL VAPOR DEPOSITION Oct 29, 2018 Abandoned
Array ( [id] => 14285765 [patent_doc_number] => 20190140167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => ANGLED SURFACE REMOVAL PROCESS AND STRUCTURE RELATING THERETO [patent_app_type] => utility [patent_app_number] => 16/175205 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175205
ANGLED SURFACE REMOVAL PROCESS AND STRUCTURE RELATING THERETO Oct 29, 2018 Pending
Array ( [id] => 17181537 [patent_doc_number] => 11158788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Atomic layer deposition and physical vapor deposition bilayer for additive patterning [patent_app_type] => utility [patent_app_number] => 16/175088 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4079 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175088
Atomic layer deposition and physical vapor deposition bilayer for additive patterning Oct 29, 2018 Issued
Array ( [id] => 18639442 [patent_doc_number] => 11764062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/175819 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175819
Method of forming semiconductor structure Oct 29, 2018 Issued
Array ( [id] => 17122085 [patent_doc_number] => 11133226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => FUSI gated device formation [patent_app_type] => utility [patent_app_number] => 16/169220 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169220
FUSI gated device formation Oct 23, 2018 Issued
Array ( [id] => 15841179 [patent_doc_number] => 20200135872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SCALED GATE CONTACT AND SOURCE/DRAIN CAP [patent_app_type] => utility [patent_app_number] => 16/169269 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169269
Scaled gate contact and source/drain cap Oct 23, 2018 Issued
Array ( [id] => 15840699 [patent_doc_number] => 20200135632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => DIE ISOLATION ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/169843 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169843
DIE ISOLATION ON A SUBSTRATE Oct 23, 2018 Abandoned
Array ( [id] => 17417224 [patent_doc_number] => 20220052128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/274777 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17274777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/274777
DISPLAY DEVICE Sep 9, 2018 Abandoned
Array ( [id] => 13741095 [patent_doc_number] => 20180375017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => MAGNETO-RESISTIVE CHIP PACKAGE INCLUDING SHIELDING STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/121266 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121266
Magneto-resistive chip package including shielding structure Sep 3, 2018 Issued
Array ( [id] => 16292694 [patent_doc_number] => 10769546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-08 [patent_title] => Microwave integrated quantum circuits with cap wafer and methods for making the same [patent_app_type] => utility [patent_app_number] => 16/113382 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 52 [patent_no_of_words] => 31425 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113382
Microwave integrated quantum circuits with cap wafer and methods for making the same Aug 26, 2018 Issued
Array ( [id] => 13629975 [patent_doc_number] => 20180366540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR DEVICES COMPRISING VIAS AND CAPACITORS [patent_app_type] => utility [patent_app_number] => 16/110615 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/110615
SEMICONDUCTOR DEVICES COMPRISING VIAS AND CAPACITORS Aug 22, 2018 Abandoned
Array ( [id] => 13613453 [patent_doc_number] => 20180358276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 16/107887 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107887
SEMICONDUCTOR DEVICE PACKAGE Aug 20, 2018 Abandoned
Array ( [id] => 13598315 [patent_doc_number] => 20180350706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SYSTEM IN PACKAGE PROCESS FLOW [patent_app_type] => utility [patent_app_number] => 16/100060 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/100060
SYSTEM IN PACKAGE PROCESS FLOW Aug 8, 2018 Abandoned
Array ( [id] => 13598777 [patent_doc_number] => 20180350937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/056564 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056564
Method for fabricating a semiconductor device Aug 6, 2018 Issued
Array ( [id] => 16308696 [patent_doc_number] => 10777504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Interconnect structure for semiconductor device and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 16/048957 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 7510 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048957
Interconnect structure for semiconductor device and methods of fabrication thereof Jul 29, 2018 Issued
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