Search

Paul Bowen

Examiner (ID: 4672)

Most Active Art Unit
2405
Art Unit(s)
2405
Total Applications
308
Issued Applications
222
Pending Applications
2
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13528423 [patent_doc_number] => 20180315754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/022713 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022713
Semiconductor device Jun 28, 2018 Issued
Array ( [id] => 15791465 [patent_doc_number] => 10629464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Plasma processing apparatus and heater temperature control method [patent_app_type] => utility [patent_app_number] => 16/013189 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11029 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013189
Plasma processing apparatus and heater temperature control method Jun 19, 2018 Issued
Array ( [id] => 16148403 [patent_doc_number] => 10707283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Organic EL element, organic EL display panel using same, and organic EL display panel manufacturing method [patent_app_type] => utility [patent_app_number] => 16/001399 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 13087 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001399
Organic EL element, organic EL display panel using same, and organic EL display panel manufacturing method Jun 5, 2018 Issued
Array ( [id] => 16567061 [patent_doc_number] => 10892438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Organic light-emitting display device having an upper substrate formed by a metal and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/985919 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7716 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15985919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/985919
Organic light-emitting display device having an upper substrate formed by a metal and method of fabricating the same May 21, 2018 Issued
Array ( [id] => 17025760 [patent_doc_number] => 20210249632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => PACKAGING COVER PLATE, ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/319576 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16319576 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/319576
Packaging cover plate, organic light-emitting diode display and manufacturing method therefor May 10, 2018 Issued
Array ( [id] => 14277695 [patent_doc_number] => 20190136132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => COMPOSITION FOR ETCHING, METHOD OF ETCHING SILICON NITRIDE LAYER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/973486 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973486
COMPOSITION FOR ETCHING, METHOD OF ETCHING SILICON NITRIDE LAYER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE May 6, 2018 Abandoned
Array ( [id] => 15092889 [patent_doc_number] => 20190341256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SELECTIVE DEPOSITION OF ETCH-STOP LAYER FOR ENHANCED PATTERNING [patent_app_type] => utility [patent_app_number] => 15/972918 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972918 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972918
Selective deposition of etch-stop layer for enhanced patterning May 6, 2018 Issued
Array ( [id] => 13543029 [patent_doc_number] => 20180323061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => Self-Aligned Triple Patterning Process Utilizing Organic Spacers [patent_app_type] => utility [patent_app_number] => 15/970168 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970168
Self-Aligned Triple Patterning Process Utilizing Organic Spacers May 2, 2018 Abandoned
Array ( [id] => 13405339 [patent_doc_number] => 20180254212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => Interconnect Structure That Avoids Insulating Layer Damage and Methods of Making the Same [patent_app_type] => utility [patent_app_number] => 15/970596 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970596
Interconnect Structure That Avoids Insulating Layer Damage and Methods of Making the Same May 2, 2018 Abandoned
Array ( [id] => 13405595 [patent_doc_number] => 20180254340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => TUNNEL FINFET WITH SELF-ALIGNED GATE [patent_app_type] => utility [patent_app_number] => 15/969226 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969226
TUNNEL FINFET WITH SELF-ALIGNED GATE May 1, 2018 Abandoned
Array ( [id] => 15092881 [patent_doc_number] => 20190341252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => METHOD FOR PATTERNING A SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/968680 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968680 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968680
Method for patterning a semiconductor structure Apr 30, 2018 Issued
Array ( [id] => 18967410 [patent_doc_number] => 11901190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Method of patterning [patent_app_type] => utility [patent_app_number] => 15/967100 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 63 [patent_no_of_words] => 6626 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967100
Method of patterning Apr 29, 2018 Issued
Array ( [id] => 16386475 [patent_doc_number] => 10811320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Footing removal in cut-metal process [patent_app_type] => utility [patent_app_number] => 15/966437 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966437 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966437
Footing removal in cut-metal process Apr 29, 2018 Issued
Array ( [id] => 14137765 [patent_doc_number] => 20190103272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Method for Manufacturing a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 15/967480 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967480
Method for manufacturing a semiconductor device Apr 29, 2018 Issued
Array ( [id] => 13378851 [patent_doc_number] => 20180240967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING [patent_app_type] => utility [patent_app_number] => 15/956376 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956376
METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING Apr 17, 2018 Abandoned
Array ( [id] => 13963107 [patent_doc_number] => 20190057898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/954912 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/954912
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE Apr 16, 2018 Abandoned
Array ( [id] => 13363935 [patent_doc_number] => 20180233507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 15/950313 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950313
SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES Apr 10, 2018 Abandoned
Array ( [id] => 13320865 [patent_doc_number] => 20180211970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED DRAIN SIDE SELECT GATE ELECTRODES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/927688 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927688 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/927688
Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof Mar 20, 2018 Issued
Array ( [id] => 14050073 [patent_doc_number] => 20190081144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/910582 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910582
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 1, 2018 Abandoned
Array ( [id] => 13528703 [patent_doc_number] => 20180315894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/909884 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909884
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME Feb 28, 2018 Abandoned
Menu