Paul Bowen

Array ( [id] => 13514513 [patent_doc_number] => 20180308799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/889009 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12849589 [patent_doc_number] => 20180175036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => Multi-Gate Device and Method of Fabrication Thereof [patent_app_type] => utility [patent_app_number] => 15/887347 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738280 [patent_doc_number] => 20180137927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Three-Dimensional Vertical One-Time-Programmable Memory Comprising No Separate Diode Layer [patent_app_type] => utility [patent_app_number] => 15/870855 [patent_app_country] => US [patent_app_date] => 2018-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12759946 [patent_doc_number] => 20180145150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS [patent_app_type] => utility [patent_app_number] => 15/859340 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14221375 [patent_doc_number] => 20190123072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => DISPLAY PANEL AND PIXEL CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 15/835463 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14317273 [patent_doc_number] => 20190148340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/835466 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13629815 [patent_doc_number] => 20180366460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => ELECTROSTATIC DISCHARGE DEVICES [patent_app_type] => utility [patent_app_number] => 15/835396 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14151707 [patent_doc_number] => 10256243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Semiconductor structure, static random access memory, and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/824830 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 10591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15791931 [patent_doc_number] => 10629698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method and structure for enabling high aspect ratio sacrificial gates [patent_app_type] => utility [patent_app_number] => 15/802095 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7661 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14801165 [patent_doc_number] => 10403592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Semiconductor packages and methods of packaging semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/726409 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 60 [patent_no_of_words] => 17191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13996073 [patent_doc_number] => 20190067194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/692439 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12236076 [patent_doc_number] => 20180068939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'REDISTRIBUTION LAYER LINES' [patent_app_type] => utility [patent_app_number] => 15/677835 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15672811 [patent_doc_number] => 10600645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Manufacturing method of gallium nitride substrate [patent_app_type] => utility [patent_app_number] => 15/662425 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7894 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14397937 [patent_doc_number] => 10312260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => GaN transistors with polysilicon layers used for creating additional components [patent_app_type] => utility [patent_app_number] => 15/655508 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 48 [patent_no_of_words] => 6011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12027072 [patent_doc_number] => 20170317171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'LEAKAGE-FREE IMPLANTATION-FREE ETSOI TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/650328 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3631 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14769603 [patent_doc_number] => 10396206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Gate cut method [patent_app_type] => utility [patent_app_number] => 15/643940 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5003 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13576705 [patent_doc_number] => 20180339901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR PROCESS [patent_app_type] => utility [patent_app_number] => 15/644430 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12141086 [patent_doc_number] => 20180019169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'BACKING SUBSTRATE STABILIZING DONOR SUBSTRATE FOR IMPLANT OR RECLAMATION' [patent_app_type] => utility [patent_app_number] => 15/643370 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4634 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12162343 [patent_doc_number] => 20180033609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'REMOVAL OF NON-CLEAVED/NON-TRANSFERRED MATERIAL FROM DONOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/643384 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12139658 [patent_doc_number] => 20180017741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/643458 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5652 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643458 [rel_patent_id] =>[rel_patent_doc_number] =>)