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Paul D. Kim

Examiner (ID: 4085)

Most Active Art Unit
3729
Art Unit(s)
3729
Total Applications
2947
Issued Applications
2453
Pending Applications
175
Abandoned Applications
347

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11331586 [patent_doc_number] => 09522822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Sensor integration with an outgassing barrier and a stable electrical signal path' [patent_app_type] => utility [patent_app_number] => 14/276445 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5921 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276445 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/276445
Sensor integration with an outgassing barrier and a stable electrical signal path May 12, 2014 Issued
Array ( [id] => 12188900 [patent_doc_number] => 20180047836 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2018-02-15 [patent_title] => 'CASCODED HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/276995 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3753 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/276995
Cascoded high voltage junction field effect transistor May 12, 2014 Issued
Array ( [id] => 9681700 [patent_doc_number] => 20140238463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'METHOD FOR PRODUCTION OF WAFER BASED SOLAR PANELS' [patent_app_type] => utility [patent_app_number] => 14/268640 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7330 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268640 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268640
Method for production of wafer based solar panels May 1, 2014 Issued
Array ( [id] => 10617971 [patent_doc_number] => 09337425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Method of manufacturing resistance change layer using irradiation of electron beam and resistive random access memory device using the same' [patent_app_type] => utility [patent_app_number] => 14/230543 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 7361 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230543
Method of manufacturing resistance change layer using irradiation of electron beam and resistive random access memory device using the same Mar 30, 2014 Issued
Array ( [id] => 9898852 [patent_doc_number] => 20150054051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/229916 [patent_app_country] => US [patent_app_date] => 2014-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229916 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229916
Semiconductor device and fabrication method Mar 29, 2014 Issued
Array ( [id] => 9771964 [patent_doc_number] => 20140295627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF LTPS TFT' [patent_app_type] => utility [patent_app_number] => 14/229337 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229337
Method for adjusting the threshold voltage of LTPS TFT Mar 27, 2014 Issued
Array ( [id] => 10208881 [patent_doc_number] => 20150093871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'ENHANCED STRESS MEMORIZATION TECHNIQUE FOR METAL GATE TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/227986 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/227986
Enhanced stress memorization technique for metal gate transistors Mar 26, 2014 Issued
Array ( [id] => 9938070 [patent_doc_number] => 08987883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Semiconductor package with multiple conductive clips' [patent_app_type] => utility [patent_app_number] => 14/192756 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2895 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192756 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192756
Semiconductor package with multiple conductive clips Feb 26, 2014 Issued
Array ( [id] => 10837898 [patent_doc_number] => 08865571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Dislocation engineering using a scanned laser' [patent_app_type] => utility [patent_app_number] => 14/174868 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2916 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174868
Dislocation engineering using a scanned laser Feb 6, 2014 Issued
Array ( [id] => 10837900 [patent_doc_number] => 08865572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Dislocation engineering using a scanned laser' [patent_app_type] => utility [patent_app_number] => 14/174869 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2917 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174869 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174869
Dislocation engineering using a scanned laser Feb 6, 2014 Issued
Array ( [id] => 11932554 [patent_doc_number] => 09799557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Semiconductor device structure with metal ring on silicon-on-insulator (SOI) substrate' [patent_app_type] => utility [patent_app_number] => 14/161208 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3617 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161208 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161208
Semiconductor device structure with metal ring on silicon-on-insulator (SOI) substrate Jan 21, 2014 Issued
Array ( [id] => 10319928 [patent_doc_number] => 20150204932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'STRUCTURE AND METHOD TO DETERMINE THROUGH SILICON VIA BUILD INTEGRITY' [patent_app_type] => utility [patent_app_number] => 14/161309 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161309
Structure and method to determine through silicon via build integrity Jan 21, 2014 Issued
Array ( [id] => 10321957 [patent_doc_number] => 20150206961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/160630 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160630
Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures Jan 21, 2014 Issued
Array ( [id] => 10129051 [patent_doc_number] => 09162874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Semiconductor structure and method forming the same' [patent_app_type] => utility [patent_app_number] => 14/160628 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160628
Semiconductor structure and method forming the same Jan 21, 2014 Issued
Array ( [id] => 10321788 [patent_doc_number] => 20150206792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHOD FOR FORMING CONDUCTING VIA AND DAMASCENE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/161258 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161258 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161258
Method for forming conducting via and damascene structure Jan 21, 2014 Issued
Array ( [id] => 10604189 [patent_doc_number] => 09324760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions' [patent_app_type] => utility [patent_app_number] => 14/159762 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159762 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159762
CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions Jan 20, 2014 Issued
Array ( [id] => 11201340 [patent_doc_number] => 09431562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Three dimensional compositional profile in CIS-based absorber layers of thin film solar cells' [patent_app_type] => utility [patent_app_number] => 14/159468 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4283 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159468
Three dimensional compositional profile in CIS-based absorber layers of thin film solar cells Jan 20, 2014 Issued
Array ( [id] => 10321755 [patent_doc_number] => 20150206759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/159457 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3319 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159457
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Jan 20, 2014 Abandoned
Array ( [id] => 10317831 [patent_doc_number] => 20150202834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'LAMINATION TRANSFER FILMS FOR FORMING ANTIREFLECTIVE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/159253 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16710 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159253
LAMINATION TRANSFER FILMS FOR FORMING ANTIREFLECTIVE STRUCTURES Jan 19, 2014 Abandoned
Array ( [id] => 10073431 [patent_doc_number] => 09111796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Semiconductor structure and layout structure for memory devices' [patent_app_type] => utility [patent_app_number] => 14/158875 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3077 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158875
Semiconductor structure and layout structure for memory devices Jan 19, 2014 Issued
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