Search

Paul D. Marcantoni

Examiner (ID: 8214, Phone: (571)272-1373 , Office: P/1731 )

Most Active Art Unit
1755
Art Unit(s)
1731, 1761, 1108, 1755, 1793, 1754
Total Applications
2409
Issued Applications
1672
Pending Applications
171
Abandoned Applications
565

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8902786 [patent_doc_number] => 20130170288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO NOISE DURING SAME ROW ACCESS' [patent_app_type] => utility [patent_app_number] => 13/339580 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11555 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339580
Dual port register file memory cell with reduced susceptibility to noise during same row access Dec 28, 2011 Issued
Array ( [id] => 8790672 [patent_doc_number] => 20130107641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/339050 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5375 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339050
Semiconductor system including semiconductor device Dec 27, 2011 Issued
Array ( [id] => 9403216 [patent_doc_number] => 08693276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Power supply, associated management unit and method' [patent_app_type] => utility [patent_app_number] => 13/339083 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339083
Power supply, associated management unit and method Dec 27, 2011 Issued
Array ( [id] => 8902775 [patent_doc_number] => 20130170278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'RESISTIVE RANDOM ACCESS MEMORY CELL AND RESISTIVE RANDOM ACCESS MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 13/338264 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2500 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13338264 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338264
Resistive random access memory cell and resistive random access memory module Dec 27, 2011 Issued
Array ( [id] => 8276500 [patent_doc_number] => 20120170376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/339092 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3720 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339092 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339092
SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF Dec 27, 2011 Abandoned
Array ( [id] => 9228565 [patent_doc_number] => 08634239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Hybrid multi-level cell programming sequences' [patent_app_type] => utility [patent_app_number] => 13/339017 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4169 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339017
Hybrid multi-level cell programming sequences Dec 27, 2011 Issued
Array ( [id] => 8682881 [patent_doc_number] => 20130051165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'SEMICONDUCTOR APPARATUS AND DATA TRANSMISSION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/339062 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4333 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339062 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339062
Semiconductor apparatus and data transmission method thereof Dec 27, 2011 Issued
Array ( [id] => 8890173 [patent_doc_number] => 20130163357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Quantifying the Read and Write Margins of Memory Bit Cells' [patent_app_type] => utility [patent_app_number] => 13/337902 [patent_app_country] => US [patent_app_date] => 2011-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13337902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/337902
Quantifying the read and write margins of memory bit cells Dec 26, 2011 Issued
Array ( [id] => 8515111 [patent_doc_number] => 20120314519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'WORD LINE DRIVING SIGNAL CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND WORD LINE DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 13/337452 [patent_app_country] => US [patent_app_date] => 2011-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4043 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13337452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/337452
Word line driving signal control circuit, semiconductor memory apparatus having the same, and word line driving method Dec 26, 2011 Issued
Array ( [id] => 8276520 [patent_doc_number] => 20120170394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'COLUMN ADDRESS CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF GENERATING COLUMN ADDRESSES' [patent_app_type] => utility [patent_app_number] => 13/337386 [patent_app_country] => US [patent_app_date] => 2011-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13337386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/337386
Column address circuit of semiconductor memory device and method of generating column addresses Dec 26, 2011 Issued
Array ( [id] => 8910886 [patent_doc_number] => 08482959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Method of programming, erasing and repairing a memory device' [patent_app_type] => utility [patent_app_number] => 13/324759 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 4384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13324759 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/324759
Method of programming, erasing and repairing a memory device Dec 12, 2011 Issued
Array ( [id] => 8039893 [patent_doc_number] => 20120069686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'LATCH TIMING ADJUSTMENT DEVICE AND MEMORY ACCESS SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/307684 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069686.pdf [firstpage_image] =>[orig_patent_app_number] => 13307684 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307684
LATCH TIMING ADJUSTMENT DEVICE AND MEMORY ACCESS SYSTEM USING THE SAME Nov 29, 2011 Abandoned
Array ( [id] => 8840313 [patent_doc_number] => 20130135941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'Enhanced Data Retention Mode for Dynamic Memories' [patent_app_type] => utility [patent_app_number] => 13/307884 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12196 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307884 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307884
Enhanced data retention mode for dynamic memories Nov 29, 2011 Issued
Array ( [id] => 8392239 [patent_doc_number] => 20120230080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'Variable Resistance Device, Semiconductor Device Including The Variable Resistance Device, And Method Of Operating The Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/307672 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12103 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307672
Variable resistance device, semiconductor device including the variable resistance device, and method of operating the semiconductor device Nov 29, 2011 Issued
Array ( [id] => 8226349 [patent_doc_number] => 20120140550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/307060 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 20452 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307060 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307060
Integrated circuit, method for driving the same, and semiconductor device Nov 29, 2011 Issued
Array ( [id] => 9456796 [patent_doc_number] => 08717813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Method and apparatus for leakage suppression in flash memory in response to external commands' [patent_app_type] => utility [patent_app_number] => 13/308266 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308266 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308266
Method and apparatus for leakage suppression in flash memory in response to external commands Nov 29, 2011 Issued
Array ( [id] => 8038053 [patent_doc_number] => 20120068758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'REFERENCE CURRENT SOURCES' [patent_app_type] => utility [patent_app_number] => 13/306848 [patent_app_country] => US [patent_app_date] => 2011-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10623 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068758.pdf [firstpage_image] =>[orig_patent_app_number] => 13306848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/306848
Reference current sources Nov 28, 2011 Issued
Array ( [id] => 8957448 [patent_doc_number] => 08503235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Nonvolatile memory with faulty cell registration' [patent_app_type] => utility [patent_app_number] => 13/298548 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13071 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298548 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298548
Nonvolatile memory with faulty cell registration Nov 16, 2011 Issued
Array ( [id] => 8295728 [patent_doc_number] => 08223524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Process variation compensated multi-chip memory package' [patent_app_type] => utility [patent_app_number] => 13/291340 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5848 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291340
Process variation compensated multi-chip memory package Nov 7, 2011 Issued
Array ( [id] => 8544900 [patent_doc_number] => 08320197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/285312 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3475 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285312
Semiconductor memory device Oct 30, 2011 Issued
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