Search

Paul Dinh

Examiner (ID: 19008, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2816
Total Applications
2010
Issued Applications
1766
Pending Applications
89
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20566144 [patent_doc_number] => 12568771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Memory cell with magnetic access selector apparatus [patent_app_type] => utility [patent_app_number] => 18/776445 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 4282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776445
Memory cell with magnetic access selector apparatus Jul 17, 2024 Issued
Array ( [id] => 19561855 [patent_doc_number] => 20240373647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SOT MRAM HAVING DIELECTRIC INTERFACIAL LAYER AND METHOD FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/774254 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774254
Sot MRAM having dielectric interfacial layer and method forming same Jul 15, 2024 Issued
Array ( [id] => 19548640 [patent_doc_number] => 20240365676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT AND ITS FABRICATION PROCESS [patent_app_type] => utility [patent_app_number] => 18/770678 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770678
Magnetic tunnel junction (MTJ) element and its fabrication process Jul 11, 2024 Issued
Array ( [id] => 19548645 [patent_doc_number] => 20240365681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/766644 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766644
Transistor, semiconductor device including the same, and manufacturing method thereof Jul 7, 2024 Issued
Array ( [id] => 19548644 [patent_doc_number] => 20240365680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => THREE-STATE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/764426 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764426
Three-state memory device Jul 4, 2024 Issued
Array ( [id] => 19517829 [patent_doc_number] => 20240349515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => LAYOUT PATTERN OF MAGNETORESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/755693 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755693 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755693
Layout pattern of magnetoresistive random access memory Jun 26, 2024 Issued
Array ( [id] => 19470575 [patent_doc_number] => 20240324245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MAGNETIC DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/731494 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731494 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731494
Magnetic device structure and methods of forming the same Jun 2, 2024 Issued
Array ( [id] => 19913769 [patent_doc_number] => 12290004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/674889 [patent_app_country] => US [patent_app_date] => 2024-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674889 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674889
Semiconductor device May 25, 2024 Issued
Array ( [id] => 19590077 [patent_doc_number] => 20240387634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS [patent_app_type] => utility [patent_app_number] => 18/669170 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669170
Nanowire transistor fabrication with hardmask layers May 19, 2024 Issued
Array ( [id] => 19392832 [patent_doc_number] => 20240282702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Assemblies having Conductive Interconnects which are Laterally and Vertically Offset Relative to One Another [patent_app_type] => utility [patent_app_number] => 18/652079 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652079
Assemblies having conductive interconnects which are laterally and vertically offset relative to one another Apr 30, 2024 Issued
Array ( [id] => 20332810 [patent_doc_number] => 12463095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor structure with a laminated layer [patent_app_type] => utility [patent_app_number] => 18/652803 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 7862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652803
Semiconductor structure with a laminated layer Apr 30, 2024 Issued
Array ( [id] => 20268600 [patent_doc_number] => 12439612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor device and manufacturing method of the semiconductor device [patent_app_type] => utility [patent_app_number] => 18/624983 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 5595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624983
Semiconductor device and manufacturing method of the semiconductor device Apr 1, 2024 Issued
Array ( [id] => 20441482 [patent_doc_number] => 12512324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Selective formation of titanium silicide and titanium nitride by hydrogen gas control [patent_app_type] => utility [patent_app_number] => 18/619633 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619633
Selective formation of titanium silicide and titanium nitride by hydrogen gas control Mar 27, 2024 Issued
Array ( [id] => 19288330 [patent_doc_number] => 20240224813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => MRAM CELL AND MRAM [patent_app_type] => utility [patent_app_number] => 18/602174 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602174
MRAM cell and MRAM Mar 11, 2024 Issued
Array ( [id] => 19271757 [patent_doc_number] => 20240215464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => METHOD OF FORMING AN INTEGRATED CIRCUIT STRUCTURE INCLUDING A RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELL [patent_app_type] => utility [patent_app_number] => 18/600826 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600826
Method of forming an integrated circuit structure including a resistive random access memory (RRAM) cell Mar 10, 2024 Issued
Array ( [id] => 19781587 [patent_doc_number] => 12230625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Integrated circuit including standard cell and filler cell [patent_app_type] => utility [patent_app_number] => 18/591089 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591089
Integrated circuit including standard cell and filler cell Feb 28, 2024 Issued
Array ( [id] => 19221530 [patent_doc_number] => 20240186234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Stack of Horizontally Extending and Vertically Overlapping Features, Methods of Forming Circuitry Components, and Methods of Forming an Array of Memory Cells [patent_app_type] => utility [patent_app_number] => 18/441767 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441767
Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells Feb 13, 2024 Issued
Array ( [id] => 19193543 [patent_doc_number] => 20240172456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SYSTEM ARCHITECTURE, STRUCTURE AND METHOD FOR HYBRID RANDOM ACCESS MEMORY IN A SYSTEM-ON-CHIP [patent_app_type] => utility [patent_app_number] => 18/420684 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420684 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420684
System architecture, structure and method for hybrid random access memory in a system-on-chip Jan 22, 2024 Issued
Array ( [id] => 19812387 [patent_doc_number] => 12243800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Package structure with lid and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/415801 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415801
Package structure with lid and method for forming the same Jan 17, 2024 Issued
Array ( [id] => 19407101 [patent_doc_number] => 20240290612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => CONFORMAL AND SELECTIVE SIN DEPOSITION [patent_app_type] => utility [patent_app_number] => 18/409549 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409549
CONFORMAL AND SELECTIVE SIN DEPOSITION Jan 9, 2024 Pending
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