Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4424071 [patent_doc_number] => 06194944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Input structure for I/O device' [patent_app_type] => 1 [patent_app_number] => 9/302634 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3405 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194944.pdf [firstpage_image] =>[orig_patent_app_number] => 302634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302634
Input structure for I/O device Apr 28, 1999 Issued
Array ( [id] => 1513499 [patent_doc_number] => 06442732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Virtual logic system for solving satisfiability problems using reconfigurable hardware' [patent_app_type] => B1 [patent_app_number] => 09/295534 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4867 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442732.pdf [firstpage_image] =>[orig_patent_app_number] => 09295534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295534
Virtual logic system for solving satisfiability problems using reconfigurable hardware Apr 20, 1999 Issued
Array ( [id] => 4361578 [patent_doc_number] => 06292042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Phase splitter' [patent_app_type] => 1 [patent_app_number] => 9/295403 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3634 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292042.pdf [firstpage_image] =>[orig_patent_app_number] => 295403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295403
Phase splitter Apr 20, 1999 Issued
Array ( [id] => 4414604 [patent_doc_number] => 06239638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'SR flip flop' [patent_app_type] => 1 [patent_app_number] => 9/254415 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1647 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239638.pdf [firstpage_image] =>[orig_patent_app_number] => 254415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/254415
SR flip flop Apr 20, 1999 Issued
Array ( [id] => 4312611 [patent_doc_number] => 06252443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Delay element using a delay locked loop' [patent_app_type] => 1 [patent_app_number] => 9/295157 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3604 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252443.pdf [firstpage_image] =>[orig_patent_app_number] => 295157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295157
Delay element using a delay locked loop Apr 19, 1999 Issued
Array ( [id] => 4339357 [patent_doc_number] => 06313679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Timing circuit' [patent_app_type] => 1 [patent_app_number] => 9/294860 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1603 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313679.pdf [firstpage_image] =>[orig_patent_app_number] => 294860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294860
Timing circuit Apr 19, 1999 Issued
Array ( [id] => 4191699 [patent_doc_number] => 06150850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Chopper type comparator' [patent_app_type] => 1 [patent_app_number] => 9/295731 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5934 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150850.pdf [firstpage_image] =>[orig_patent_app_number] => 295731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295731
Chopper type comparator Apr 19, 1999 Issued
Array ( [id] => 4423947 [patent_doc_number] => 06194926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Operation timing controllable system' [patent_app_type] => 1 [patent_app_number] => 9/291173 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3758 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194926.pdf [firstpage_image] =>[orig_patent_app_number] => 291173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291173
Operation timing controllable system Apr 13, 1999 Issued
Array ( [id] => 4241391 [patent_doc_number] => 06118307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Switched capacitor sorter based on magnitude' [patent_app_type] => 1 [patent_app_number] => 9/257719 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2824 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118307.pdf [firstpage_image] =>[orig_patent_app_number] => 257719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257719
Switched capacitor sorter based on magnitude Mar 1, 1999 Issued
Array ( [id] => 4256020 [patent_doc_number] => 06137338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Low resistance input protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/259578 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137338.pdf [firstpage_image] =>[orig_patent_app_number] => 259578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259578
Low resistance input protection circuit Feb 28, 1999 Issued
Array ( [id] => 4256020 [patent_doc_number] => 06137338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Low resistance input protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/259578 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137338.pdf [firstpage_image] =>[orig_patent_app_number] => 259578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259578
Low resistance input protection circuit Feb 28, 1999 Issued
Array ( [id] => 4091594 [patent_doc_number] => 06163192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Negative pulse edge triggered flip-flop' [patent_app_type] => 1 [patent_app_number] => 9/259148 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163192.pdf [firstpage_image] =>[orig_patent_app_number] => 259148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259148
Negative pulse edge triggered flip-flop Feb 25, 1999 Issued
Array ( [id] => 4304180 [patent_doc_number] => 06198335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method and apparatus to drive the coil of a magnetic write head' [patent_app_type] => 1 [patent_app_number] => 9/258100 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5445 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198335.pdf [firstpage_image] =>[orig_patent_app_number] => 258100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258100
Method and apparatus to drive the coil of a magnetic write head Feb 24, 1999 Issued
Array ( [id] => 4413389 [patent_doc_number] => 06172534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Gain control arrangement and method' [patent_app_type] => 1 [patent_app_number] => 9/257418 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3004 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172534.pdf [firstpage_image] =>[orig_patent_app_number] => 257418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257418
Gain control arrangement and method Feb 24, 1999 Issued
Array ( [id] => 4245010 [patent_doc_number] => 06144232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Chopper type voltage comparing circuit capable of correctly determining output polarity, and voltage comparing method' [patent_app_type] => 1 [patent_app_number] => 9/256293 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10286 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144232.pdf [firstpage_image] =>[orig_patent_app_number] => 256293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256293
Chopper type voltage comparing circuit capable of correctly determining output polarity, and voltage comparing method Feb 23, 1999 Issued
Array ( [id] => 1506016 [patent_doc_number] => 06466059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Sense amplifier for low voltage memories' [patent_app_type] => B1 [patent_app_number] => 09/249834 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466059.pdf [firstpage_image] =>[orig_patent_app_number] => 09249834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249834
Sense amplifier for low voltage memories Feb 11, 1999 Issued
Array ( [id] => 4246478 [patent_doc_number] => 06091277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Input buffer circuit for semiconductor IC circuit' [patent_app_type] => 1 [patent_app_number] => 9/233128 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1763 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091277.pdf [firstpage_image] =>[orig_patent_app_number] => 233128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233128
Input buffer circuit for semiconductor IC circuit Jan 18, 1999 Issued
Array ( [id] => 4197974 [patent_doc_number] => 06130568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Threshold voltage compensation circuit' [patent_app_type] => 1 [patent_app_number] => 9/231670 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3948 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130568.pdf [firstpage_image] =>[orig_patent_app_number] => 231670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231670
Threshold voltage compensation circuit Jan 14, 1999 Issued
Array ( [id] => 4224500 [patent_doc_number] => 06111440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Circuit for generating interleaved ramped voltage signals having uniform, controlled maximum amplitude' [patent_app_type] => 1 [patent_app_number] => 9/231046 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4105 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111440.pdf [firstpage_image] =>[orig_patent_app_number] => 231046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231046
Circuit for generating interleaved ramped voltage signals having uniform, controlled maximum amplitude Jan 13, 1999 Issued
Array ( [id] => 6138609 [patent_doc_number] => 20020000839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SENSE AMPLIFIER' [patent_app_type] => new [patent_app_number] => 09/225665 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3163 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000839.pdf [firstpage_image] =>[orig_patent_app_number] => 09225665 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225665
Sense amplifier Jan 4, 1999 Issued
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