
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20267180
[patent_doc_number] => 12438180
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Battery formation and grading device
[patent_app_type] => utility
[patent_app_number] => 18/466291
[patent_app_country] => US
[patent_app_date] => 2023-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1197
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466291
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/466291 | Battery formation and grading device | Sep 12, 2023 | Issued |
Array
(
[id] => 19195952
[patent_doc_number] => 11993177
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-05-28
[patent_title] => Predictive temperature regulation
[patent_app_type] => utility
[patent_app_number] => 18/458072
[patent_app_country] => US
[patent_app_date] => 2023-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9530
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458072
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458072 | Predictive temperature regulation | Aug 28, 2023 | Issued |
Array
(
[id] => 18832840
[patent_doc_number] => 20230401367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => DRL-BASED CONTROL LOGIC DESIGN METHOD FOR CONTINUOUS MICROFLUIDIC BIOCHIPS
[patent_app_type] => utility
[patent_app_number] => 18/238562
[patent_app_country] => US
[patent_app_date] => 2023-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7342
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238562
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/238562 | DRL-BASED CONTROL LOGIC DESIGN METHOD FOR CONTINUOUS MICROFLUIDIC BIOCHIPS | Aug 27, 2023 | Pending |
Array
(
[id] => 19802887
[patent_doc_number] => 20250068812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES
[patent_app_type] => utility
[patent_app_number] => 18/456042
[patent_app_country] => US
[patent_app_date] => 2023-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5799
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456042
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/456042 | IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES | Aug 24, 2023 | Pending |
Array
(
[id] => 18811185
[patent_doc_number] => 20230385521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 18/447455
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447455
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447455 | Rule check violation prediction systems and methods | Aug 9, 2023 | Issued |
Array
(
[id] => 19459301
[patent_doc_number] => 12099793
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Rule check violation prediction systems and methods
[patent_app_type] => utility
[patent_app_number] => 18/446745
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 15439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446745
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446745 | Rule check violation prediction systems and methods | Aug 8, 2023 | Issued |
Array
(
[id] => 19639067
[patent_doc_number] => 12169675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Automatic generation of layouts for analog integrated circuits
[patent_app_type] => utility
[patent_app_number] => 18/362574
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 10413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362574
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362574 | Automatic generation of layouts for analog integrated circuits | Jul 30, 2023 | Issued |
Array
(
[id] => 18940972
[patent_doc_number] => 20240036111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => CHIP VERIFICATION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/361471
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12840
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361471 | CHIP VERIFICATION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM | Jul 27, 2023 | Pending |
Array
(
[id] => 19748283
[patent_doc_number] => 20250036848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => SYSTEMS AND METHODS FOR MACHINE LEARNING BASED VOLTAGE DROP PREDICTION FOR A 3D STACKED DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/227225
[patent_app_country] => US
[patent_app_date] => 2023-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7832
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227225
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/227225 | SYSTEMS AND METHODS FOR MACHINE LEARNING BASED VOLTAGE DROP PREDICTION FOR A 3D STACKED DEVICE | Jul 26, 2023 | Pending |
Array
(
[id] => 19747132
[patent_doc_number] => 20250035697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => BIAS CAUSE REDUCTION FOR LOCALIZING CONSTRAINTS
[patent_app_type] => utility
[patent_app_number] => 18/358353
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358353
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/358353 | BIAS CAUSE REDUCTION FOR LOCALIZING CONSTRAINTS | Jul 24, 2023 | Pending |
Array
(
[id] => 18925805
[patent_doc_number] => 20240028809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => INTEGRATED CIRCUIT DESIGN, CONTEXTUAL CELLS, DESIGN MIGRATION, AND ASSOCIATED METHODS
[patent_app_type] => utility
[patent_app_number] => 18/356484
[patent_app_country] => US
[patent_app_date] => 2023-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5332
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356484
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/356484 | INTEGRATED CIRCUIT DESIGN, CONTEXTUAL CELLS, DESIGN MIGRATION, AND ASSOCIATED METHODS | Jul 20, 2023 | Pending |
Array
(
[id] => 18811182
[patent_doc_number] => 20230385518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/354377
[patent_app_country] => US
[patent_app_date] => 2023-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23452
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354377
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/354377 | Integrated circuit and method of forming the same | Jul 17, 2023 | Issued |
Array
(
[id] => 19712728
[patent_doc_number] => 20250022870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => SMALL DUMMY POLY PATTERN INSERTION IN SMALL BORDER REGIONS
[patent_app_type] => utility
[patent_app_number] => 18/349965
[patent_app_country] => US
[patent_app_date] => 2023-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11202
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349965
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/349965 | SMALL DUMMY POLY PATTERN INSERTION IN SMALL BORDER REGIONS | Jul 10, 2023 | Pending |
Array
(
[id] => 18743977
[patent_doc_number] => 20230352965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => PORTABLE CHARGER
[patent_app_type] => utility
[patent_app_number] => 18/350490
[patent_app_country] => US
[patent_app_date] => 2023-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350490
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/350490 | Portable charger | Jul 10, 2023 | Issued |
Array
(
[id] => 19424522
[patent_doc_number] => 12083918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Vehicle
[patent_app_type] => utility
[patent_app_number] => 18/350237
[patent_app_country] => US
[patent_app_date] => 2023-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 8120
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350237
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/350237 | Vehicle | Jul 10, 2023 | Issued |
Array
(
[id] => 20117621
[patent_doc_number] => 12367330
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Integrated circuit design method and system
[patent_app_type] => utility
[patent_app_number] => 18/347928
[patent_app_country] => US
[patent_app_date] => 2023-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 5598
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347928
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/347928 | Integrated circuit design method and system | Jul 5, 2023 | Issued |
Array
(
[id] => 19157011
[patent_doc_number] => 20240149718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => MULTILEVEL MOTOR DRIVE WITH INTEGRATED BATTERY CHARGER
[patent_app_type] => utility
[patent_app_number] => 18/347835
[patent_app_country] => US
[patent_app_date] => 2023-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3720
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347835
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/347835 | Multilevel motor drive with integrated battery charger | Jul 5, 2023 | Issued |
Array
(
[id] => 19353639
[patent_doc_number] => 12054066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Systems and methods for identifying characteristics of electric vehicles
[patent_app_type] => utility
[patent_app_number] => 18/348272
[patent_app_country] => US
[patent_app_date] => 2023-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 13764
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348272
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/348272 | Systems and methods for identifying characteristics of electric vehicles | Jul 5, 2023 | Issued |
Array
(
[id] => 20009212
[patent_doc_number] => 20250147434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => Metrology in the Presence of CMOS Under Array (CUA) Structures Utilizing Model-Less Machine Learning
[patent_app_type] => utility
[patent_app_number] => 18/217262
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2215
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/217262 | Metrology in the Presence of CMOS Under Array (CUA) Structures Utilizing Model-Less Machine Learning | Jun 29, 2023 | Pending |
Array
(
[id] => 19190222
[patent_doc_number] => 20240169135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => REINFORCEMENT LEARNING (RL) BASED CHIP DESIGN OPTIMIZATION USING TRAINED GRAPH CONVOLUTIONAL NETWORKS (GCN) FOR ULTRA-FAST COST FUNCTION CALCULATION
[patent_app_type] => utility
[patent_app_number] => 18/216510
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216510
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/216510 | REINFORCEMENT LEARNING (RL) BASED CHIP DESIGN OPTIMIZATION USING TRAINED GRAPH CONVOLUTIONAL NETWORKS (GCN) FOR ULTRA-FAST COST FUNCTION CALCULATION | Jun 28, 2023 | Pending |