Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14980733 [patent_doc_number] => 10444274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Method of inspecting a specimen and system thereof [patent_app_type] => utility [patent_app_number] => 16/025869 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7122 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/025869
Method of inspecting a specimen and system thereof Jul 1, 2018 Issued
Array ( [id] => 13486223 [patent_doc_number] => 20180294654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => STORAGE BATTERY PACK, METHOD FOR CONTROLLING STORAGE BATTERY PACK, AND METHOD FOR CONTROLLING INFORMATION TERMINAL [patent_app_type] => utility [patent_app_number] => 16/009346 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009346
Storage battery pack, method for controlling storage battery pack, and method for controlling information terminal Jun 14, 2018 Issued
Array ( [id] => 14299297 [patent_doc_number] => 10289776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/980999 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980999 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980999
Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit May 15, 2018 Issued
Array ( [id] => 15919929 [patent_doc_number] => 10657207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-19 [patent_title] => Inter-cell bridge defect diagnosis [patent_app_type] => utility [patent_app_number] => 15/972812 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972812
Inter-cell bridge defect diagnosis May 6, 2018 Issued
Array ( [id] => 16232964 [patent_doc_number] => 10740516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Modifying circuits to prevent redundant switching [patent_app_type] => utility [patent_app_number] => 15/970979 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970979
Modifying circuits to prevent redundant switching May 3, 2018 Issued
Array ( [id] => 15091031 [patent_doc_number] => 20190340326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => PREVENTING CORNER VIOLATIONS IN FILL REGION OF LAYOUT USING EXCLUSION LAYER [patent_app_type] => utility [patent_app_number] => 15/971280 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971280
Preventing corner violations in fill region of layout using exclusion layer May 3, 2018 Issued
Array ( [id] => 13569519 [patent_doc_number] => 20180336307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => METHOD FOR DESIGNING AN INTEGRATED CIRCUIT, AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/971079 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971079
Method for designing an integrated circuit, and method of manufacturing the integrated circuit May 3, 2018 Issued
Array ( [id] => 15091027 [patent_doc_number] => 20190340324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => FRONT-END-OF-LINE SHAPE MERGING CELL PLACEMENT AND OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/969841 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969841
Front-end-of-line shape merging cell placement and optimization May 2, 2018 Issued
Array ( [id] => 13361881 [patent_doc_number] => 20180232480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => DESIGN AWARE VARIABLE FILL PATTERN GENERATOR [patent_app_type] => utility [patent_app_number] => 15/949460 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949460
Aware variable fill pattern generator Apr 9, 2018 Issued
Array ( [id] => 16065807 [patent_doc_number] => 10691856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => System design flow with runtime customizable circuits [patent_app_type] => utility [patent_app_number] => 15/943519 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 31608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943519
System design flow with runtime customizable circuits Apr 1, 2018 Issued
Array ( [id] => 13467883 [patent_doc_number] => 20180285484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => Concurrent Testbench and Software Driven Verification [patent_app_type] => utility [patent_app_number] => 15/943423 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943423
Concurrent testbench and software driven verification Apr 1, 2018 Issued
Array ( [id] => 16146241 [patent_doc_number] => 10706192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Voltage reconciliation in multi-level power managed systems [patent_app_type] => utility [patent_app_number] => 15/941176 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10805 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941176 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941176
Voltage reconciliation in multi-level power managed systems Mar 29, 2018 Issued
Array ( [id] => 16263587 [patent_doc_number] => 10755023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Circuit timing analysis [patent_app_type] => utility [patent_app_number] => 15/940963 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940963
Circuit timing analysis Mar 28, 2018 Issued
Array ( [id] => 15680073 [patent_doc_number] => 20200094700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SYSTEM AND METHOD FOR CHARGING ELECTRIC VEHICLES [patent_app_type] => utility [patent_app_number] => 16/494895 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16494895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/494895
System and method for charging electric vehicles Mar 21, 2018 Issued
Array ( [id] => 13665527 [patent_doc_number] => 10162927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Methods for redistributing cell densities in layout area of IC [patent_app_type] => utility [patent_app_number] => 15/915172 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3188 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915172
Methods for redistributing cell densities in layout area of IC Mar 7, 2018 Issued
Array ( [id] => 13356145 [patent_doc_number] => 20180229612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => ELECTRIC VEHICLE CHARGING INTERFACE [patent_app_type] => utility [patent_app_number] => 15/890534 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890534 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890534
Electric vehicle charging interface Feb 6, 2018 Issued
Array ( [id] => 15285027 [patent_doc_number] => 10515178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Merged pillar structures and method of generating layout diagram of same [patent_app_type] => utility [patent_app_number] => 15/882188 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882188
Merged pillar structures and method of generating layout diagram of same Jan 28, 2018 Issued
Array ( [id] => 16217537 [patent_doc_number] => 10733351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => Generating width spacing patterns for multiple patterning processes using instances [patent_app_type] => utility [patent_app_number] => 15/872724 [patent_app_country] => US [patent_app_date] => 2018-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15872724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/872724
Generating width spacing patterns for multiple patterning processes using instances Jan 15, 2018 Issued
Array ( [id] => 16346681 [patent_doc_number] => 20200311332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => PIN MUST-CONNECTS FOR IMPROVED PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/649800 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649800
Pin must-connects for improved performance Dec 26, 2017 Issued
Array ( [id] => 12694645 [patent_doc_number] => 20180123381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Peak Power Caching in a Wireless Power System [patent_app_type] => utility [patent_app_number] => 15/852764 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852764
Peak power caching in a wireless power system Dec 21, 2017 Issued
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