Search

Paul Dinh

Examiner (ID: 2326, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2816, 2851
Total Applications
1996
Issued Applications
1754
Pending Applications
98
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18496833 [patent_doc_number] => 20230219431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => CONTROLLERS, DEVICES, AND METHODS FOR PERFORMING POWER QUALITY CONTROL USING DIRECT CURRENT FAST CHARGING DEVICES [patent_app_type] => utility [patent_app_number] => 18/120462 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120462
Controllers, devices, and methods for performing power quality control using direct current fast charging devices Mar 12, 2023 Issued
Array ( [id] => 18800770 [patent_doc_number] => 11833917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-05 [patent_title] => EV charger with fault ride through capability [patent_app_type] => utility [patent_app_number] => 18/115268 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 62 [patent_no_of_words] => 23452 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115268
EV charger with fault ride through capability Feb 27, 2023 Issued
Array ( [id] => 18454715 [patent_doc_number] => 20230195995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SYSTEMS AND METHODS OF ELIMINATING CONNECTIVITY MISMATCHES IN A MASK LAYOUT BLOCK [patent_app_type] => utility [patent_app_number] => 18/110644 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110644
SYSTEMS AND METHODS OF ELIMINATING CONNECTIVITY MISMATCHES IN A MASK LAYOUT BLOCK Feb 15, 2023 Abandoned
Array ( [id] => 18599265 [patent_doc_number] => 20230274065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => USING MACHINE LEARNING TO PRODUCE ROUTES [patent_app_type] => utility [patent_app_number] => 18/110345 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110345
USING MACHINE LEARNING TO PRODUCE ROUTES Feb 14, 2023 Pending
Array ( [id] => 18438715 [patent_doc_number] => 20230186010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELLS, METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT, AND COMPUTING SYSTEM FOR PERFORMING THE METHOD [patent_app_type] => utility [patent_app_number] => 18/167421 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167421
Integrated circuit including standard cells, method of manufacturing the integrated circuit, and computing system for performing the method Feb 9, 2023 Issued
Array ( [id] => 18554320 [patent_doc_number] => 20230252333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND APPARATUS FOR PROCESSING AND MEASURING PHOTONIC QUBIT SIGNALS [patent_app_type] => utility [patent_app_number] => 18/105080 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105080
METHOD AND APPARATUS FOR PROCESSING AND MEASURING PHOTONIC QUBIT SIGNALS Feb 1, 2023 Pending
Array ( [id] => 18554320 [patent_doc_number] => 20230252333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND APPARATUS FOR PROCESSING AND MEASURING PHOTONIC QUBIT SIGNALS [patent_app_type] => utility [patent_app_number] => 18/105080 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105080
METHOD AND APPARATUS FOR PROCESSING AND MEASURING PHOTONIC QUBIT SIGNALS Feb 1, 2023 Pending
Array ( [id] => 19144944 [patent_doc_number] => 20240143880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/160593 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160593
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM Jan 26, 2023 Pending
Array ( [id] => 19347785 [patent_doc_number] => 20240256749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES [patent_app_type] => utility [patent_app_number] => 18/102490 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102490
RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES Jan 26, 2023 Pending
Array ( [id] => 19144944 [patent_doc_number] => 20240143880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/160593 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160593
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM Jan 26, 2023 Pending
Array ( [id] => 18686365 [patent_doc_number] => 11782094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Battery state estimation method and apparatus [patent_app_type] => utility [patent_app_number] => 18/099422 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099422
Battery state estimation method and apparatus Jan 19, 2023 Issued
Array ( [id] => 18515096 [patent_doc_number] => 20230231372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => VEHICLE CHARGING SYSTEM FOR AN ELECTRIC VEHICLE HAVING ARC DETECTION [patent_app_type] => utility [patent_app_number] => 18/155823 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155823
VEHICLE CHARGING SYSTEM FOR AN ELECTRIC VEHICLE HAVING ARC DETECTION Jan 17, 2023 Pending
Array ( [id] => 19317695 [patent_doc_number] => 20240239236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => ELECTRIC VEHICLE ENERGY STORAGE SYSTEMS INCLUDING DC-DC POWER CONVERTERS OPERABLE IN SELECTED OPERATING MODES [patent_app_type] => utility [patent_app_number] => 18/097379 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097379
ELECTRIC VEHICLE ENERGY STORAGE SYSTEMS INCLUDING DC-DC POWER CONVERTERS OPERABLE IN SELECTED OPERATING MODES Jan 15, 2023 Pending
Array ( [id] => 18386423 [patent_doc_number] => 11657206 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-23 [patent_title] => Method for semiconductor design based on artificial intelligence [patent_app_type] => utility [patent_app_number] => 18/154340 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15748 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154340
Method for semiconductor design based on artificial intelligence Jan 12, 2023 Issued
Array ( [id] => 18934349 [patent_doc_number] => 11886783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Simulation system for semiconductor process and simulation method thereof [patent_app_type] => utility [patent_app_number] => 18/153573 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 9785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153573
Simulation system for semiconductor process and simulation method thereof Jan 11, 2023 Issued
Array ( [id] => 19305824 [patent_doc_number] => 20240234404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => INTEGRATED CIRCUIT AND SYSTEM FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/153250 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153250
INTEGRATED CIRCUIT AND SYSTEM FOR FABRICATING THE SAME Jan 10, 2023 Pending
Array ( [id] => 19305824 [patent_doc_number] => 20240234404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => INTEGRATED CIRCUIT AND SYSTEM FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/153250 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153250
INTEGRATED CIRCUIT AND SYSTEM FOR FABRICATING THE SAME Jan 10, 2023 Pending
Array ( [id] => 18734951 [patent_doc_number] => 11803685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-31 [patent_title] => Layout design method, chip and terminal of power device [patent_app_type] => utility [patent_app_number] => 18/152268 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152268
Layout design method, chip and terminal of power device Jan 9, 2023 Issued
Array ( [id] => 19303917 [patent_doc_number] => 20240232497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Method for Generating Placement and Routing for an Integrated Circuit (IC) [patent_app_type] => utility [patent_app_number] => 18/150716 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150716
Method for Generating Placement and Routing for an Integrated Circuit (IC) Jan 4, 2023 Pending
Array ( [id] => 19303917 [patent_doc_number] => 20240232497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Method for Generating Placement and Routing for an Integrated Circuit (IC) [patent_app_type] => utility [patent_app_number] => 18/150716 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150716
Method for Generating Placement and Routing for an Integrated Circuit (IC) Jan 4, 2023 Pending
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