Paul Dinh

Array ( [id] => 14492979 [patent_doc_number] => 10333293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Method for increasing pad efficiency and robustness [patent_app_type] => utility [patent_app_number] => 15/605569 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9762 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15925869 [patent_doc_number] => 10660195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Printed circuit board and electronic component package including same [patent_app_type] => utility [patent_app_number] => 16/098380 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4517 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16098380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16652400 [patent_doc_number] => 10929582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Circuit validation for circuits comprising multiple possible variants for individual components [patent_app_type] => utility [patent_app_number] => 16/089408 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5535 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16089408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14177921 [patent_doc_number] => 10262981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/465167 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 15418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12256180 [patent_doc_number] => 09928326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Efficient deployment of table lookup (TLU) in an enterprise-level scalable circuit simulation architecture' [patent_app_type] => utility [patent_app_number] => 15/452913 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4590 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709250 [patent_doc_number] => 20170177749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'EFFICIENT DEPLOYMENT OF TABLE LOOKUP (TLU) IN AN ENTERPRISE-LEVEL SCALABLE CIRCUIT SIMULATION ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/452908 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14299313 [patent_doc_number] => 10289784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Determination of clock path delays and implementation of a circuit design [patent_app_type] => utility [patent_app_number] => 15/432537 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13361883 [patent_doc_number] => 20180232481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => DATA PROCESSING SYSTEM TO IMPLEMENT WIRING/SILICON BLOCKAGES VIA PARAMETERIZED CELLS [patent_app_type] => utility [patent_app_number] => 15/431061 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14365053 [patent_doc_number] => 10303833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Parallelizing timing-based operations for circuit designs [patent_app_type] => utility [patent_app_number] => 15/429014 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14615263 [patent_doc_number] => 10360334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library [patent_app_type] => utility [patent_app_number] => 15/428449 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13130675 [patent_doc_number] => 10083271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Minimizing harmful effects caused by reticle defects by re-arranging IC layout locally [patent_app_type] => utility [patent_app_number] => 15/427728 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 6748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14705067 [patent_doc_number] => 10380283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Functional verification with machine learning [patent_app_type] => utility [patent_app_number] => 15/426434 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6307 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15013317 [patent_doc_number] => 10452806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-22 [patent_title] => Generating a colored track pattern of non-uniform width from a sparse set of tracks [patent_app_type] => utility [patent_app_number] => 15/425679 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5185 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14062379 [patent_doc_number] => 10235484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Automatic timing-sensitive circuit extraction [patent_app_type] => utility [patent_app_number] => 15/425642 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11952295 [patent_doc_number] => 20170256446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL AND ELECTRONIC DESIGN AUTOMATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/425593 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14556221 [patent_doc_number] => 10346572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Inclusion and configuration of a transaction converter circuit block within an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/424684 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12892747 [patent_doc_number] => 20180189424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => TOOL TO CREATE A RECONFIGURABLE INTERCONNECT FRAMEWORK [patent_app_type] => utility [patent_app_number] => 15/423292 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13333133 [patent_doc_number] => 20180218104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => METHODS AND APPARATUS FOR AUTOMATICALLY IMPLEMENTING A COMPENSATING RESET FOR RETIMED CIRCUITRY [patent_app_type] => utility [patent_app_number] => 15/422971 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14887407 [patent_doc_number] => 10423747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Method and apparatus for supporting temporal virtualization on a target device [patent_app_type] => utility [patent_app_number] => 15/422834 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 9596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13333125 [patent_doc_number] => 20180218100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => Reliability Verification Based On Combining Voltage Propagation With Simulation [patent_app_type] => utility [patent_app_number] => 15/420448 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420448 [rel_patent_id] =>[rel_patent_doc_number] =>)