
Paul Dinh
Examiner (ID: 10982, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2816 |
| Total Applications | 2011 |
| Issued Applications | 1767 |
| Pending Applications | 89 |
| Abandoned Applications | 176 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11385097
[patent_doc_number] => 20170011153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'Validating Variation of Timing Constraint Measurements'
[patent_app_type] => utility
[patent_app_number] => 14/833069
[patent_app_country] => US
[patent_app_date] => 2015-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6602
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833069
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/833069 | Validating variation of timing constraint measurements | Aug 21, 2015 | Issued |
Array
(
[id] => 11423931
[patent_doc_number] => 20170032075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-02
[patent_title] => 'System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing'
[patent_app_type] => utility
[patent_app_number] => 14/810428
[patent_app_country] => US
[patent_app_date] => 2015-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3967
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810428
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/810428 | System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing | Jul 26, 2015 | Issued |
Array
(
[id] => 11403971
[patent_doc_number] => 20170024509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'OPTICAL CRITICAL DIMENSION TARGET DESIGN'
[patent_app_type] => utility
[patent_app_number] => 14/809061
[patent_app_country] => US
[patent_app_date] => 2015-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5580
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809061
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/809061 | Optical critical dimension target design | Jul 23, 2015 | Issued |
Array
(
[id] => 10717021
[patent_doc_number] => 20160063168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM'
[patent_app_type] => utility
[patent_app_number] => 14/808506
[patent_app_country] => US
[patent_app_date] => 2015-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5694
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14808506
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/808506 | Pattern-based FPGA logic block and clustering algorithm | Jul 23, 2015 | Issued |
Array
(
[id] => 11403967
[patent_doc_number] => 20170024506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT LAYOUT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 14/807869
[patent_app_country] => US
[patent_app_date] => 2015-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3193
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807869
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/807869 | Method for optimizing an integrated circuit layout design | Jul 22, 2015 | Issued |
Array
(
[id] => 11385098
[patent_doc_number] => 20170011154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'Validating Variation of Timing Constraint Measurements'
[patent_app_type] => utility
[patent_app_number] => 14/792779
[patent_app_country] => US
[patent_app_date] => 2015-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6602
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792779
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/792779 | Validating variation of timing constraint measurements | Jul 6, 2015 | Issued |
Array
(
[id] => 11637159
[patent_doc_number] => 09659134
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Computing device and method for determining wiring paths on printed circuit board'
[patent_app_type] => utility
[patent_app_number] => 14/791663
[patent_app_country] => US
[patent_app_date] => 2015-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2575
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791663
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/791663 | Computing device and method for determining wiring paths on printed circuit board | Jul 5, 2015 | Issued |
Array
(
[id] => 10189023
[patent_doc_number] => 09218444
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-22
[patent_title] => 'Approximate circuits for increased reliability'
[patent_app_type] => utility
[patent_app_number] => 14/792109
[patent_app_country] => US
[patent_app_date] => 2015-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5332
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792109
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/792109 | Approximate circuits for increased reliability | Jul 5, 2015 | Issued |
Array
(
[id] => 11385104
[patent_doc_number] => 20170011161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'TIMING ANALYSIS METHOD FOR DIGITAL CIRCUIT DESIGN AND SYSTEM THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/791495
[patent_app_country] => US
[patent_app_date] => 2015-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4254
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791495
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/791495 | Timing analysis method for digital circuit design and system thereof | Jul 5, 2015 | Issued |
Array
(
[id] => 11359384
[patent_doc_number] => 09536038
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-01-03
[patent_title] => 'Method and algorithm for functional critical paths selection and critical path sensors and controller insertion'
[patent_app_type] => utility
[patent_app_number] => 14/791446
[patent_app_country] => US
[patent_app_date] => 2015-07-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 10423
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791446
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/791446 | Method and algorithm for functional critical paths selection and critical path sensors and controller insertion | Jul 3, 2015 | Issued |
Array
(
[id] => 12113950
[patent_doc_number] => 09869939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Lithography process'
[patent_app_type] => utility
[patent_app_number] => 14/733719
[patent_app_country] => US
[patent_app_date] => 2015-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4575
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733719
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/733719 | Lithography process | Jun 7, 2015 | Issued |
Array
(
[id] => 10391875
[patent_doc_number] => 20150276882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'MONITORING APPARATUS, MONITORING CONTROL APPARATUS, POWER SUPPLY APPARATUS, MONITORING METHOD, MONITORING CONTROL METHOD, POWER STORAGE SYSTEM, ELECTRONIC APPARATUS, MOTOR-DRIVEN VEHICLE, AND ELECTRIC POWER SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/722752
[patent_app_country] => US
[patent_app_date] => 2015-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13036
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722752
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/722752 | Monitoring apparatus, monitoring control apparatus, power supply apparatus, monitoring method, monitoring control method, power storage system, electronic apparatus, motor-driven vehicle, and electric power system | May 26, 2015 | Issued |
Array
(
[id] => 11294271
[patent_doc_number] => 20160344203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-24
[patent_title] => 'CURRENT BALANCING DEVICE FOR PARALLEL BATTERY CELLS IN AN ELECTRIFIED VEHICLE'
[patent_app_type] => utility
[patent_app_number] => 14/714878
[patent_app_country] => US
[patent_app_date] => 2015-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3217
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14714878
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/714878 | Current balancing device for parallel battery cells in an electrified vehicle | May 17, 2015 | Issued |
Array
(
[id] => 11274228
[patent_doc_number] => 20160336775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'USB Flash Memory Unit with Charging Arrangement'
[patent_app_type] => utility
[patent_app_number] => 14/714274
[patent_app_country] => US
[patent_app_date] => 2015-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2389
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14714274
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/714274 | USB Flash Memory Unit with Charging Arrangement | May 15, 2015 | Abandoned |
Array
(
[id] => 10818160
[patent_doc_number] => 20160164323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'SUPPORTING DEVICE FOR PORTABLE ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/713835
[patent_app_country] => US
[patent_app_date] => 2015-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3052
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14713835
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/713835 | Supporting device for portable electronic device | May 14, 2015 | Issued |
Array
(
[id] => 11124414
[patent_doc_number] => 20160321388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'METHOD FOR LIBRARY HAVING BASE CELL AND VT-RELATED CELL'
[patent_app_type] => utility
[patent_app_number] => 14/700563
[patent_app_country] => US
[patent_app_date] => 2015-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6962
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700563
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/700563 | Method for library having base cell and VT-related | Apr 29, 2015 | Issued |
Array
(
[id] => 11577895
[patent_doc_number] => 09633159
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-25
[patent_title] => 'Method and system for performing distributed timing signoff and optimization'
[patent_app_type] => utility
[patent_app_number] => 14/701193
[patent_app_country] => US
[patent_app_date] => 2015-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6926
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701193
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/701193 | Method and system for performing distributed timing signoff and optimization | Apr 29, 2015 | Issued |
Array
(
[id] => 11680563
[patent_doc_number] => 09679094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-13
[patent_title] => 'Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types'
[patent_app_type] => utility
[patent_app_number] => 14/699405
[patent_app_country] => US
[patent_app_date] => 2015-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 12524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699405
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/699405 | Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types | Apr 28, 2015 | Issued |
Array
(
[id] => 10991836
[patent_doc_number] => 20160188781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-30
[patent_title] => 'METHODS FOR RETARGETING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING RETARGETED LAYOUTS'
[patent_app_type] => utility
[patent_app_number] => 14/699705
[patent_app_country] => US
[patent_app_date] => 2015-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4234
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699705
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/699705 | Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts | Apr 28, 2015 | Issued |
Array
(
[id] => 11124410
[patent_doc_number] => 20160321385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'CLOCK PLACEMENT FOR PROGRAMMABLE LOGIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/698785
[patent_app_country] => US
[patent_app_date] => 2015-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8063
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14698785
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/698785 | Clock placement for programmable logic devices | Apr 27, 2015 | Issued |