Search

Paul Dinh

Examiner (ID: 10982, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2816
Total Applications
2011
Issued Applications
1767
Pending Applications
89
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9714581 [patent_doc_number] => 08839184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-16 [patent_title] => 'Computer-assisted router for a programmable device' [patent_app_type] => utility [patent_app_number] => 14/204440 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204440 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/204440
Computer-assisted router for a programmable device Mar 10, 2014 Issued
Array ( [id] => 10562752 [patent_doc_number] => 09286430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-15 [patent_title] => 'Hierarchical visualization-based analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/196971 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 8617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/196971
Hierarchical visualization-based analysis of integrated circuits Mar 3, 2014 Issued
Array ( [id] => 10363513 [patent_doc_number] => 20150248518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'MINIMIZING HARMFUL EFFECTS CAUSED BY RETICLE DEFECTS BY RE-ARRANGING IC LAYOUT LOCALLY' [patent_app_type] => utility [patent_app_number] => 14/195006 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195006 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195006
Minimizing harmful effects caused by reticle defects by re-arranging IC layout locally Mar 2, 2014 Issued
Array ( [id] => 10358624 [patent_doc_number] => 20150243630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'DIE STACKING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/187644 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187644
Die stacking apparatus and method Feb 23, 2014 Issued
Array ( [id] => 11818316 [patent_doc_number] => 09722283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Using effective C-rates to determine inaccessible capacities of batteries' [patent_app_type] => utility [patent_app_number] => 14/184167 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/184167
Using effective C-rates to determine inaccessible capacities of batteries Feb 18, 2014 Issued
Array ( [id] => 11200219 [patent_doc_number] => 09430433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'Multi-layer distributed network' [patent_app_type] => utility [patent_app_number] => 14/175924 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14175924 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/175924
Multi-layer distributed network Feb 6, 2014 Issued
Array ( [id] => 10335666 [patent_doc_number] => 20150220671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'EFFICIENT DEPLOYMENT OF TABLE LOOKUP (TLU) IN AN ENTERPRISE-LEVEL SCALABLE CIRCUIT SIMULATION ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/170126 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170126 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/170126
Efficient deployment of table lookup (TLU) in an enterprise-level scalable circuit simulation architecture Jan 30, 2014 Issued
Array ( [id] => 11321001 [patent_doc_number] => 09519743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Optimal stacked transistor placement to increase single event transient robustness' [patent_app_type] => utility [patent_app_number] => 14/169840 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5807 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/169840
Optimal stacked transistor placement to increase single event transient robustness Jan 30, 2014 Issued
Array ( [id] => 10328182 [patent_doc_number] => 20150213186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'TIMING DRIVEN CLOCK TREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/168363 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8546 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168363 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/168363
Timing driven clock tree synthesis Jan 29, 2014 Issued
Array ( [id] => 10328165 [patent_doc_number] => 20150213169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'REGRESSION NEAREST NEIGHBOR ANALYSIS FOR STATISTICAL FUNCTIONAL COVERAGE' [patent_app_type] => utility [patent_app_number] => 14/168817 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168817 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/168817
Regression nearest neighbor analysis for statistical functional coverage Jan 29, 2014 Issued
Array ( [id] => 10328170 [patent_doc_number] => 20150213174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'REGRESSION SIGNATURE FOR STATISTICAL FUNCTIONAL COVERAGE' [patent_app_type] => utility [patent_app_number] => 14/168884 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/168884
Regression signature for statistical functional coverage Jan 29, 2014 Issued
Array ( [id] => 10569471 [patent_doc_number] => 09292641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Timing bottleneck analysis across pipelines to guide optimization with useful skew' [patent_app_type] => utility [patent_app_number] => 14/141280 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141280
Timing bottleneck analysis across pipelines to guide optimization with useful skew Dec 25, 2013 Issued
Array ( [id] => 9564053 [patent_doc_number] => 20140181766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'MULTI-MODE SCHEDULER FOR CLOCK TREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/141270 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3078 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141270
Multi-mode scheduler for clock tree synthesis Dec 25, 2013 Issued
Array ( [id] => 9564052 [patent_doc_number] => 20140181765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'LOOK-UP BASED BUFFER TREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/139590 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4993 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139590
Look-up based buffer tree synthesis Dec 22, 2013 Issued
Array ( [id] => 10556430 [patent_doc_number] => 09280631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Performing OPC on hardware or software platforms with GPU' [patent_app_type] => utility [patent_app_number] => 14/137656 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7644 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137656 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137656
Performing OPC on hardware or software platforms with GPU Dec 19, 2013 Issued
Array ( [id] => 10637701 [patent_doc_number] => 09355205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Method and apparatus of a three dimensional integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/137679 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137679 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137679
Method and apparatus of a three dimensional integrated circuit Dec 19, 2013 Issued
Array ( [id] => 10411541 [patent_doc_number] => 20150296550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'MULTI FUNCTION DOCKING MODULE FOR A PRESSURE SUPPORT THERAPY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/443430 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/443430
Multi function docking module for a pressure support therapy system Dec 10, 2013 Issued
Array ( [id] => 9548886 [patent_doc_number] => 20140173534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES' [patent_app_type] => utility [patent_app_number] => 14/094491 [patent_app_country] => US [patent_app_date] => 2013-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6006 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14094491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/094491
RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES Dec 1, 2013 Abandoned
Array ( [id] => 10066608 [patent_doc_number] => 09105466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/084823 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6941 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084823 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084823
Integrated circuit Nov 19, 2013 Issued
Array ( [id] => 9367966 [patent_doc_number] => 20140077839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/084509 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3894 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084509
Clock signal networks for structured ASIC devices Nov 18, 2013 Issued
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