Search

Paul Dinh

Examiner (ID: 10982, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2816
Total Applications
2011
Issued Applications
1767
Pending Applications
89
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10618441 [patent_doc_number] => 09337897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Power line communication system' [patent_app_type] => utility [patent_app_number] => 14/001421 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5189 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001421 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001421
Power line communication system Jan 31, 2012 Issued
Array ( [id] => 8782008 [patent_doc_number] => 20130103983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'BDD-BASED FUNCTIONAL COVERAGE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/360811 [patent_app_country] => US [patent_app_date] => 2012-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360811 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/360811
BDD-based functional coverage analysis Jan 29, 2012 Issued
Array ( [id] => 8929924 [patent_doc_number] => 20130185684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/348850 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348850 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348850
Integrated circuit design method and system Jan 11, 2012 Issued
Array ( [id] => 8918222 [patent_doc_number] => 20130179848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'SYSTEM AND METHOD OF CIRCUIT LAYOUT FOR MULTIPLE CELLS' [patent_app_type] => utility [patent_app_number] => 13/343980 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13343980 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343980
System and method of circuit layout for multiple cells Jan 4, 2012 Issued
Array ( [id] => 8716255 [patent_doc_number] => 08402408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Register retiming technique' [patent_app_type] => utility [patent_app_number] => 13/338776 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13338776 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/338776
Register retiming technique Dec 27, 2011 Issued
Array ( [id] => 9218554 [patent_doc_number] => 08631364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'Constraining VLSI circuits' [patent_app_type] => utility [patent_app_number] => 13/337170 [patent_app_country] => US [patent_app_date] => 2011-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7791 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13337170 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/337170
Constraining VLSI circuits Dec 25, 2011 Issued
Array ( [id] => 10009745 [patent_doc_number] => 09053267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Noise analysis using timing models' [patent_app_type] => utility [patent_app_number] => 13/335320 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4470 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335320
Noise analysis using timing models Dec 21, 2011 Issued
Array ( [id] => 11301156 [patent_doc_number] => 09509171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method and apparatus for optimizing standby power consumption and providing user indications in WPC based wireless charging system' [patent_app_type] => utility [patent_app_number] => 14/362912 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6926 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14362912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/362912
Method and apparatus for optimizing standby power consumption and providing user indications in WPC based wireless charging system Dec 14, 2011 Issued
Array ( [id] => 10909820 [patent_doc_number] => 20140312836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING ELECTRONIC DEVICES WIRELESS CHARGING USING INERTIAL SENSORS' [patent_app_type] => utility [patent_app_number] => 14/362812 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4020 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14362812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/362812
Method and apparatus for improving electronics devices wireless charging using inertial sensors Dec 13, 2011 Issued
Array ( [id] => 8214302 [patent_doc_number] => 20120131524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 13/301601 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 18808 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131524.pdf [firstpage_image] =>[orig_patent_app_number] => 13301601 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301601
Method and mechanism for identifying and tracking shape connectivity Nov 20, 2011 Issued
Array ( [id] => 8830991 [patent_doc_number] => 20130132036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'SCATTEROMETRY MEASUREMENT OF LINE EDGE ROUGHNESS IN THE BRIGHT FIELD' [patent_app_type] => utility [patent_app_number] => 13/300120 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13300120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/300120
Scatterometry measurement of line edge roughness in the bright field Nov 17, 2011 Issued
Array ( [id] => 10594036 [patent_doc_number] => 09315110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Device for inductive transfer of electrical energy and method for use thereof' [patent_app_type] => utility [patent_app_number] => 13/993469 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4611 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993469
Device for inductive transfer of electrical energy and method for use thereof Nov 8, 2011 Issued
Array ( [id] => 8189466 [patent_doc_number] => 20120117525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'Translating a User Design in A Configurable IC for Debugging the User Design' [patent_app_type] => utility [patent_app_number] => 13/291087 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 24880 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117525.pdf [firstpage_image] =>[orig_patent_app_number] => 13291087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291087
Translating a user design in a configurable IC for debugging the user design Nov 6, 2011 Issued
Array ( [id] => 7770631 [patent_doc_number] => 20120036489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'DESIGN AND VERIFICATION OF 3D INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/274091 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036489.pdf [firstpage_image] =>[orig_patent_app_number] => 13274091 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/274091
Verification of 3D integrated circuits Oct 13, 2011 Issued
Array ( [id] => 9242367 [patent_doc_number] => 08607172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Integrated circuits and methods of designing the same' [patent_app_type] => utility [patent_app_number] => 13/267310 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267310
Integrated circuits and methods of designing the same Oct 5, 2011 Issued
Array ( [id] => 9326364 [patent_doc_number] => 08661401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Interactive graphical pin assignment' [patent_app_type] => utility [patent_app_number] => 13/245662 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13245662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/245662
Interactive graphical pin assignment Sep 25, 2011 Issued
Array ( [id] => 7671720 [patent_doc_number] => 20110320989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'MINIMAL LEAKAGE-POWER STANDARD CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/226012 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3368 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13226012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/226012
Minimal leakage-power standard cell library Sep 5, 2011 Issued
Array ( [id] => 8044861 [patent_doc_number] => 20120072161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'THERMAL-ANALYSIS-MODEL GENERATING APPARATUS, THERMAL-ANALYSIS-MODEL GENERATING PROGRAM, THERMAL-ANALYSIS-MODEL GENERATING METHOD, AND THERMAL ANALYSIS APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/219020 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20120072161.pdf [firstpage_image] =>[orig_patent_app_number] => 13219020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219020
Thermal-analysis-model generating apparatus, non-transitory computer-readable storage medium, thermal-analysis-model generating method, and thermal analysis apparatus Aug 25, 2011 Issued
Array ( [id] => 9458708 [patent_doc_number] => 08719735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Optimizing lithographic mask for manufacturability in efficient manner' [patent_app_type] => utility [patent_app_number] => 13/183070 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13183070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183070
Optimizing lithographic mask for manufacturability in efficient manner Jul 13, 2011 Issued
Array ( [id] => 7571039 [patent_doc_number] => 20110266695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD' [patent_app_type] => utility [patent_app_number] => 13/180840 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2907 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266695.pdf [firstpage_image] =>[orig_patent_app_number] => 13180840 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180840
SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD Jul 11, 2011 Abandoned
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