Search

Paul Dinh

Examiner (ID: 11086, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2816, 2851, 2825
Total Applications
2013
Issued Applications
1768
Pending Applications
90
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9458708 [patent_doc_number] => 08719735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Optimizing lithographic mask for manufacturability in efficient manner' [patent_app_type] => utility [patent_app_number] => 13/183070 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13183070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183070
Optimizing lithographic mask for manufacturability in efficient manner Jul 13, 2011 Issued
Array ( [id] => 7571039 [patent_doc_number] => 20110266695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD' [patent_app_type] => utility [patent_app_number] => 13/180840 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2907 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266695.pdf [firstpage_image] =>[orig_patent_app_number] => 13180840 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180840
SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD Jul 11, 2011 Abandoned
Array ( [id] => 9527708 [patent_doc_number] => 08751999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Component placement tool for printed circuit board' [patent_app_type] => utility [patent_app_number] => 13/176310 [patent_app_country] => US [patent_app_date] => 2011-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6804 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/176310
Component placement tool for printed circuit board Jul 4, 2011 Issued
Array ( [id] => 8568864 [patent_doc_number] => 20120331435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS' [patent_app_type] => utility [patent_app_number] => 13/170020 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11290 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/170020
Integrated circuit design using through silicon vias Jun 26, 2011 Issued
Array ( [id] => 9169982 [patent_doc_number] => 08595676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'BDD-based functional modeling' [patent_app_type] => utility [patent_app_number] => 13/163700 [patent_app_country] => US [patent_app_date] => 2011-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9870 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163700
BDD-based functional modeling Jun 18, 2011 Issued
Array ( [id] => 9348292 [patent_doc_number] => 08667455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Hierarchical visualization-based analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/134700 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 8594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13134700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/134700
Hierarchical visualization-based analysis of integrated circuits Jun 12, 2011 Issued
Array ( [id] => 8518121 [patent_doc_number] => 20120317529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'Rapid Estimation of Temperature Rise in Wires Due to Joule Heating' [patent_app_type] => utility [patent_app_number] => 13/157980 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13157980 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/157980
Rapid estimation of temperature rise in wires due to Joule heating Jun 9, 2011 Issued
Array ( [id] => 8337435 [patent_doc_number] => 20120204132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'METHOD AND APPARATUS FOR CONFIGURABLE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/152242 [patent_app_country] => US [patent_app_date] => 2011-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 6243 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13152242 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/152242
Method and apparatus for configurable systems Jun 1, 2011 Issued
Array ( [id] => 9062995 [patent_doc_number] => 08549450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Methods and software for determining net bounds for placing and routing' [patent_app_type] => utility [patent_app_number] => 13/149230 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149230 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149230
Methods and software for determining net bounds for placing and routing May 30, 2011 Issued
Array ( [id] => 9077618 [patent_doc_number] => 08555210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Systems and methods for stochastic models of mask process variability' [patent_app_type] => utility [patent_app_number] => 13/098150 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3333 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098150 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098150
Systems and methods for stochastic models of mask process variability Apr 28, 2011 Issued
Array ( [id] => 8414791 [patent_doc_number] => 20120242291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 13/511052 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4975 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13511052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/511052
Battery pack Apr 27, 2011 Issued
Array ( [id] => 7809180 [patent_doc_number] => 20120060134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'Wiring Design Support Apparatus and Wiring Design Support Method' [patent_app_type] => utility [patent_app_number] => 13/094680 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3974 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060134.pdf [firstpage_image] =>[orig_patent_app_number] => 13094680 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094680
Wiring Design Support Apparatus and Wiring Design Support Method Apr 25, 2011 Abandoned
Array ( [id] => 9242362 [patent_doc_number] => 08607168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Contour alignment for model calibration' [patent_app_type] => utility [patent_app_number] => 13/092440 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5198 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092440
Contour alignment for model calibration Apr 21, 2011 Issued
Array ( [id] => 8540599 [patent_doc_number] => 08316327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Methods of optical proximity correction' [patent_app_type] => utility [patent_app_number] => 13/089955 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089955
Methods of optical proximity correction Apr 18, 2011 Issued
Array ( [id] => 8959179 [patent_doc_number] => 08504973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Systems and methods for generating a test environment and test system surrounding a design of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/088300 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12165 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088300 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088300
Systems and methods for generating a test environment and test system surrounding a design of an integrated circuit Apr 14, 2011 Issued
Array ( [id] => 7479943 [patent_doc_number] => 20110248318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD AND APPARATUS FOR CONFIGURABLE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/085366 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3081 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248318.pdf [firstpage_image] =>[orig_patent_app_number] => 13085366 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/085366
Method and apparatus for configurable systems Apr 11, 2011 Issued
Array ( [id] => 8355154 [patent_doc_number] => 08250499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Integrated circuit with on-board power utilization information' [patent_app_type] => utility [patent_app_number] => 13/084107 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/084107
Integrated circuit with on-board power utilization information Apr 10, 2011 Issued
Array ( [id] => 5960940 [patent_doc_number] => 20110185327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'DELAY CALCULATING METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/078411 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9897 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185327.pdf [firstpage_image] =>[orig_patent_app_number] => 13078411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/078411
DELAY CALCULATING METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT Mar 31, 2011 Abandoned
Array ( [id] => 10184935 [patent_doc_number] => 09214619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'Method of improving energy consumption efficiency and mobile terminal thereof, and use of thermo-electric conversion module' [patent_app_type] => utility [patent_app_number] => 13/811385 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3454 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13811385 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/811385
Method of improving energy consumption efficiency and mobile terminal thereof, and use of thermo-electric conversion module Mar 28, 2011 Issued
Array ( [id] => 6020839 [patent_doc_number] => 20110225557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/048650 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225557.pdf [firstpage_image] =>[orig_patent_app_number] => 13048650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048650
HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM Mar 14, 2011 Abandoned
Menu