
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8343233
[patent_doc_number] => 08245159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-14
[patent_title] => 'Gradient based search mechanism for optimizing photolithograph masks'
[patent_app_type] => utility
[patent_app_number] => 12/536090
[patent_app_country] => US
[patent_app_date] => 2009-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 7486
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12536090
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/536090 | Gradient based search mechanism for optimizing photolithograph masks | Aug 4, 2009 | Issued |
Array
(
[id] => 8297454
[patent_doc_number] => 08225254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-17
[patent_title] => 'Delay period analyzing apparatus, delay period analyzing method, and delay period analyzing program'
[patent_app_type] => utility
[patent_app_number] => 12/534970
[patent_app_country] => US
[patent_app_date] => 2009-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10749
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12534970
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/534970 | Delay period analyzing apparatus, delay period analyzing method, and delay period analyzing program | Aug 3, 2009 | Issued |
Array
(
[id] => 5491956
[patent_doc_number] => 20090293027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'Connection consistency check processing method, cable selection processing method, design confirmation processing device and recording medium that records design confirmation processing program'
[patent_app_type] => utility
[patent_app_number] => 12/458840
[patent_app_country] => US
[patent_app_date] => 2009-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 16759
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0293/20090293027.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458840
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458840 | Connection consistency check processing method, cable selection processing method, design confirmation processing device and recording medium that records design confirmation processing program | Jul 22, 2009 | Issued |
Array
(
[id] => 5376033
[patent_doc_number] => 20090313594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'Relative Positioning of Circuit Elements in Circuit Design'
[patent_app_type] => utility
[patent_app_number] => 12/506131
[patent_app_country] => US
[patent_app_date] => 2009-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12085
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0313/20090313594.pdf
[firstpage_image] =>[orig_patent_app_number] => 12506131
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/506131 | Relative positioning of circuit elements in circuit design | Jul 19, 2009 | Issued |
Array
(
[id] => 8172601
[patent_doc_number] => RE043393
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2012-05-15
[patent_title] => 'Method and system for creating and programming an adaptive computing engine'
[patent_app_type] => reissue
[patent_app_number] => 12/504093
[patent_app_country] => US
[patent_app_date] => 2009-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4265
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/043/RE043393.pdf
[firstpage_image] =>[orig_patent_app_number] => 12504093
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/504093 | Method and system for creating and programming an adaptive computing engine | Jul 15, 2009 | Issued |
Array
(
[id] => 6141086
[patent_doc_number] => 20110010683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'Trace Routing According To Freeform Sketches'
[patent_app_type] => utility
[patent_app_number] => 12/499600
[patent_app_country] => US
[patent_app_date] => 2009-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6960
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20110010683.pdf
[firstpage_image] =>[orig_patent_app_number] => 12499600
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/499600 | Trace routing according to freeform sketches | Jul 7, 2009 | Issued |
Array
(
[id] => 8319799
[patent_doc_number] => 08234595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-31
[patent_title] => 'Method of designing a mask layout'
[patent_app_type] => utility
[patent_app_number] => 12/498470
[patent_app_country] => US
[patent_app_date] => 2009-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 7177
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12498470
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/498470 | Method of designing a mask layout | Jul 6, 2009 | Issued |
Array
(
[id] => 5476100
[patent_doc_number] => 20090249266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects'
[patent_app_type] => utility
[patent_app_number] => 12/482276
[patent_app_country] => US
[patent_app_date] => 2009-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17706
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20090249266.pdf
[firstpage_image] =>[orig_patent_app_number] => 12482276
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/482276 | Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects | Jun 9, 2009 | Issued |
Array
(
[id] => 8366760
[patent_doc_number] => 08255841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-28
[patent_title] => 'Performing OPC on hardware or software platforms with GPU'
[patent_app_type] => utility
[patent_app_number] => 12/480958
[patent_app_country] => US
[patent_app_date] => 2009-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7517
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12480958
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/480958 | Performing OPC on hardware or software platforms with GPU | Jun 8, 2009 | Issued |
Array
(
[id] => 5392899
[patent_doc_number] => 20090210212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'Validating One or More Circuits Using One or More Grids'
[patent_app_type] => utility
[patent_app_number] => 12/433182
[patent_app_country] => US
[patent_app_date] => 2009-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7300
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20090210212.pdf
[firstpage_image] =>[orig_patent_app_number] => 12433182
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/433182 | Validating one or more circuits using one or more grids | Apr 29, 2009 | Issued |
Array
(
[id] => 8985284
[patent_doc_number] => 08516414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Behavioral synthesis device, behavioral synthesis method, and computer program product'
[patent_app_type] => utility
[patent_app_number] => 12/409856
[patent_app_country] => US
[patent_app_date] => 2009-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6597
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12409856
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/409856 | Behavioral synthesis device, behavioral synthesis method, and computer program product | Mar 23, 2009 | Issued |
Array
(
[id] => 8220419
[patent_doc_number] => 08196074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-05
[patent_title] => 'Heuristic clustering of circuit elements in a circuit design'
[patent_app_type] => utility
[patent_app_number] => 12/406439
[patent_app_country] => US
[patent_app_date] => 2009-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7675
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/196/08196074.pdf
[firstpage_image] =>[orig_patent_app_number] => 12406439
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/406439 | Heuristic clustering of circuit elements in a circuit design | Mar 17, 2009 | Issued |
Array
(
[id] => 5377803
[patent_doc_number] => 20090189642
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-30
[patent_title] => 'Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions'
[patent_app_type] => utility
[patent_app_number] => 12/403094
[patent_app_country] => US
[patent_app_date] => 2009-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5577
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20090189642.pdf
[firstpage_image] =>[orig_patent_app_number] => 12403094
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/403094 | Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions | Mar 11, 2009 | Abandoned |
Array
(
[id] => 5504267
[patent_doc_number] => 20090164955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/372518
[patent_app_country] => US
[patent_app_date] => 2009-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8635
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20090164955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12372518
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/372518 | METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME | Feb 16, 2009 | Abandoned |
Array
(
[id] => 8273247
[patent_doc_number] => 08214770
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Multilayer OPC for design aware manufacturing'
[patent_app_type] => utility
[patent_app_number] => 12/357648
[patent_app_country] => US
[patent_app_date] => 2009-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5941
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12357648
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/357648 | Multilayer OPC for design aware manufacturing | Jan 21, 2009 | Issued |
Array
(
[id] => 4600861
[patent_doc_number] => 07984402
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-07-19
[patent_title] => 'Two-pass method for implementing a flexible testbench'
[patent_app_type] => utility
[patent_app_number] => 12/352429
[patent_app_country] => US
[patent_app_date] => 2009-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 5975
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/984/07984402.pdf
[firstpage_image] =>[orig_patent_app_number] => 12352429
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/352429 | Two-pass method for implementing a flexible testbench | Jan 11, 2009 | Issued |
Array
(
[id] => 5332883
[patent_doc_number] => 20090113360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL'
[patent_app_type] => utility
[patent_app_number] => 12/348070
[patent_app_country] => US
[patent_app_date] => 2009-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4356
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20090113360.pdf
[firstpage_image] =>[orig_patent_app_number] => 12348070
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/348070 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jan 1, 2009 | Issued |
Array
(
[id] => 7780237
[patent_doc_number] => 08122397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-21
[patent_title] => 'Method and system for mapping source elements to destination elements as interconnect routing assignments'
[patent_app_type] => utility
[patent_app_number] => 12/331218
[patent_app_country] => US
[patent_app_date] => 2008-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3957
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/122/08122397.pdf
[firstpage_image] =>[orig_patent_app_number] => 12331218
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/331218 | Method and system for mapping source elements to destination elements as interconnect routing assignments | Dec 8, 2008 | Issued |
Array
(
[id] => 5286156
[patent_doc_number] => 20090099831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'METHOD FOR GENERATING AND EVALUATING A TABLE MODEL FOR CIRCUIT SIMULATION'
[patent_app_type] => utility
[patent_app_number] => 12/328595
[patent_app_country] => US
[patent_app_date] => 2008-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8304
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20090099831.pdf
[firstpage_image] =>[orig_patent_app_number] => 12328595
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328595 | Method for generating and evaluating a table model for circuit simulation | Dec 3, 2008 | Issued |
Array
(
[id] => 8260128
[patent_doc_number] => 08209643
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-06-26
[patent_title] => 'Method and mechanism for determining shape connectivity'
[patent_app_type] => utility
[patent_app_number] => 12/325242
[patent_app_country] => US
[patent_app_date] => 2008-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 34
[patent_no_of_words] => 10194
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12325242
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/325242 | Method and mechanism for determining shape connectivity | Nov 29, 2008 | Issued |